Dynamic Engineering PMC-BiSerial-III HW2 User Manual page 48

Specifications
Host Interface:
Serial Interface:
TX Data rates generated:
TX Options
RX Data rates accepted:
Software Interface:
Initialization:
Access Modes:
Wait States:
Interrupt:
DMA:
Onboard Options:
Interface Options:
Dimensions:
Construction:
(PMC) PCI Mezzanine Card - 32 bit, 33 MHz
Up to 8 manchester encoded serial interfaces. 16-bit word size, MSB first,
multiple words, CRC, embedded length, label.
Up to 6 Full Duplex SDLC serial interfaces. 16-bit word size, LSB first.
Up to 12 Full Duplex Asynchronous serial interfaces. 16-bit word size, 8
data bits, 1 start-bit, 1 stop-bit, no parity LSB first.
40 MHz oscillator used to generate 80 MHz. 800 Khz, 3.2 MHz, 10 MHz
and 40 Mhz are generated to provide TX and RX reference rates. 5 MHz
and 400 KHz I/O frequencies supported via software selection.
SDLC – PLL clock A for custom frequencies.
Asynchronous – 312.5 Kbps or PLL clock B (16x data rate) for custom
frequencies.
Tristate or transmit IDLE pattern between messages, append post amble
pattern, calculate and append CRC in hardware, interrupt on a packet
basis.
Continuous at 5 MHz. or 400 KHz for HW1 interface. SDLC and
asynchronous rates programmable
Control Registers, Status Ports, Dual Port RAM, Driver Available
Hardware Reset forces all registers to 0.
LW boundary Space (see memory map)
1 for all addresses
TX interrupt at end of packet or message transmission
RX interrupt at end of packet or message reception
Software interrupt
I2O interrupts
No DMA Support implemented at this time
All Options are Software Programmable
68 pin twisted pair cable
68 screw terminal block interface
Standard Single PMC Module.
FR4 Multi-Layer Printed Circuit, Through Hole and Surface Mount
Components. Programmable parts are socketed.
Embedded Solutions
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