Bis3_Chan_Mode; Figure 23 Pmc Biserial-Iii Channel Mode Control Register - Dynamic Engineering PMC-BiSerial-III HW2 User Manual

BIS3_CHAN_MODE

[$C8] BiSerial III HW2 Channel Mode Control Register
DATA BIT
31-16
15-14
13-12
11-10
9-8
7-6
5-4
3-2
1-0
FIGURE 23
The first two channel blocks (channels 0 - 7) are "hard-wired" to HW1 mode. The
remaining six channel blocks can each be configured to be one full-duplex SDLC
channel using four I/O lines and four DPR blocks (2 each for transmit and receive) or
two full-duplex asynchronous channels each using two I/O lines and two DPR blocks (1
each for transmit and receive).
The mode definitions for each channel block are as follows:
One SDLC channel
Two ASYNC channels
Four HW1 channels
Channel Mode Control Register
DESCRIPTION
Spare
Channel 31-28 mode (bit 15 = '0')
Channel 27-24 mode (bit 13 = '0')
Channel 23-20 mode (bit 11 = '0')
Channel 19-16 mode (bit 9 = '0')
Channel 15-12 mode (bit 7 = '0')
Channel 11-8 mode (bit 5 = '0')
Channel 7-4 mode = "10"
Channel 3-0 mode = "10"
PMC BISERIAL-III CHANNEL MODE CONTROL REGISTER
= "00"
= "01"
= "10"
Embedded Solutions
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