Dynamic Engineering PMC-BiSerial-III HW2 User Manual page 31

32 channel bi-directional manchester, sdlc and asynchronous interface pmc module
Table of Contents

Advertisement

Receive Interrupt Enable : When this bit is a one the receiver interrupt is enabled.
The interrupt will occur at the end of a message transmission, which is determined by
the detection of at least eleven bit-periods of a high level on the input line after a
message has started. When this bit is a zero the interrupt status will still be latched, but
will not cause an interrupt to occur. The receive interrupt is mapped to the second or
fourth interrupt line in its channel block depending on whether it is the first or second
asynchronous interface in that block.
Load Receive Start Address : When this bit is a one the value in the address input
field is loaded into the receiver start-address register. When this bit is a zero no action
is taken.
Load Transmit Start Address : When this bit is a one the value in the address input
field is loaded into the transmitter start-address register. When this bit is a zero no
action is taken.
Load Transmit End Address : When this bit is a one the value in the address input
field is loaded into the transmitter end-address register. When this bit is a zero no
action is taken.
Clock Select : When this bit is a one the PLL B clock input is selected as the 16x clock
for asynchronous character decoding. When this bit is a zero the 5 MHz clock is used
(312.5 Kbps). The clock is divided by sixteen to create the transmit bit clock.
Address Input : This field is used with the three load address bits to specify address
boundaries for the transmit and receive state machines.
Receive End Address : This field represents the address that the last received
character is stored in. Note that this is a byte address, the lower two bits indicate the
byte (0 – 3) in the appropriate long-word where the last character was stored
Framing Error : When a one is read in this bit position, it indicates that a framing error
has been detected. This will occur if the stop bit for a received character is not a one.
This bit is latched and is cleared by writing a one back in this bit position.
Embedded Solutions
Page 31 of 50

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the PMC-BiSerial-III HW2 and is the answer not in the manual?

Table of Contents