Table 30: Timing parameters
Parameter
Description
T(sync)
PCM_SYNC cycle time
T(synch)
PCM_SYNC high time
T(syncl)
PCM_SYNC low time
T(clk)
PCM_CLK cycle time
T(clkh)
PCM_CLK high time
T(clkl)
PCM_CLK low time
PCM_SYNC setup time high before falling edge of
T(susync)
PCM_CLK
PCM_SYNC hold time after falling edge of
T(hsync)
PCM_CLK
PCM_DIN setup time before falling edge of
T(sudin)
PCM_CLK
PCM_DIN hold time after falling edge of
T(hdin)
PCM_CLK
SIM5320AL_User Manual_V1.01
Figure 33: Synchrony timing
Figure 34: EXT CODEC to MODULE timing
Figure 35: MODULE to EXT CODEC timing
Smart Machine Smart Decision
Min
–
400
–
–
–
–
60
60
50
10
47
Typ
Max Unit
125
–
μs
500
–
ns
124.5 –
μs
488
–
ns
244
–
ns
244
–
ns
–
–
ns
–
–
ns
–
–
ns
–
–
ns
2014-08-20
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