Control Loop Gain; Voltage And Current Stress - Analog Devices ADP1071-1EVALZ User Manual

UG-1384
24V LOAD STEP
0mA TO 400mA
1
4
+5.5V
+24V
AT NO
LOAD
3
CH1 500mA CH2 1.00V
CH3 5.00V CH4 5.00V
Figure 9. Cross Regulation with Load Step at a +24 V Rail When +5.5 V and
−15 V Rails at No Load

CONTROL LOOP GAIN

The loop gain can be measured via a network analyzer. The
small signal perturbation is injected at R19 and at the 5.5 V test
points. Figure 10 shows the loop gain of the system.
15
10
5
0
–5
–10
–15
–20
–25
–30
–35
1 1k
FREQUENCY (Hz)
Figure 10. Loop Gain Measurement, Crossover Frequency = 432.33 Hz, Phase
Margin = 91.07°, Gain Margin = 13.51 dB

VOLTAGE AND CURRENT STRESS

The drain to source voltage of the main switch is clamped by
the transient voltage suppressor (TVS) diode on the evaluation
board. The peak drain to source voltage occurs at the maximum
input voltage. The drain to source voltages at full load are shown
in Figure 11. The peak drain to source voltage is 114 V, and the
peak primary current is 2.2 A.
–15V
AT NO
LOAD
A CH1 135mA
250
PHASE
MAGNITUDE
200
150
100
50
0
–50
–100
–150
–200
–250
10k 2 100k
Rev. 0 | Page 6 of 13
ADP1071-1EVALZ
1
4
CH1 20.0V
Ω
CH4 2.0A B
Figure 11. MOSFET Drain to Source Voltages at 32 V
The peak reverse voltage stress on the secondary diodes are
measured in Figure 12 to Figure 14 under the same condition
as in Figure 11. For +5.5 V, +24 V, and −15 V rails, the diode
voltage stress is −19.5 V, −72.4 V, and +48 V, respectively.
1
4
CH1 5.00V
Ω
CH4 2.0A B
W
Figure 12. Peak Diode Voltage Stress on a 5.5 V Rail at 32 V
1
4
CH1 20.0V
CH4 2.0A Ω
Figure 13. Peak Diode Voltage Stress on a 24 V Rail at 32 V
User Guide
M10.0µs A CH1 75.6V
T 0.0ns
W
Input and Full Load
DC
M10.0µs A CH1 –16.0V
T 0.0ns
Input and Full
DC
Load
M10.0µs A CH1 –57.6V
T 0.0s
B
W
Input and Full
DC
Load