Chapter 8 Reset Function; Separated Reset Functions; External Reset Circuitry; External Reset Circuitry With Pull-Down Resistor - NEC V850ES/DJ2 User Manual

8.1 Separated Reset Functions

The reset functions of the FG2 and the MTRC are separated to each other. Therefore the application
has to coordinate the reset states.

8.2 External Reset Circuitry

To control the Reset state of the MTRC it is recommended, to connect the MTRESET pin to an output
port of the FG2.
Remarks: 1. It is not possible to connect the MTRESET pin of the MTRC and RESET pin of the FG2
together.
(If the FG2 comes into Reset state during a serial transmission via the CSIB1, the com-
munication can't be restarted. Because of the independent clock supply of the MTRC, it
will wait for the continuation of the broken communication. But if the Reset state of the
F_Line is released, the MTRC SFRs would be re-initialized with a totally new transmis-
sion of the CSIB1 again. Therefore the communication will be left out of synchroniza-
tion.)
2. During a Power save mode the signal at MTRESET pin should be high to remain the
MTRC in operation mode (but switched off Ring Oscillator). Otherwise the MTRC will
consume in reset mode more current via the PU/PD resistors at the internal connection
pins (please refer to 2. on page 70).

8.2.1 External reset circuitry with pull-down resistor

Figure 8-1: External Reset Circuitry with Pull-Down Resistor
RESET IC
This circuitry is the best choose for safety applications, but consumes more power in power save
modes.
If the FG2 will be reset via an internal (LVI or WD) or external function (RESET), the Pxx pin will be set
into its reset mode (input) and the pull down resistor will set the MTRC into reset state, too.
In power save mode a continuous current will be consumed via R

Chapter 8 Reset Function

RESET
V850ES/DJ2
Preliminary User's Manual U17763EE1V1UD00
R
PD
Pxx
V850ES/FG2
.
PD
MTRESET
MTRC
128