External Reset Circuitry With Pull-Up Resistor - NEC V850ES/DJ2 User Manual

Chapter 8 Reset Function

8.2.2 External reset circuitry with pull-up resistor

Figure 8-2: External Reset Circuitry with Pull-Up Resistor
MTV
DD
R
PU
C
Pxx MTRESET
V850ES/FG2 MTRC
RESET
RESET IC
V850ES/DJ2
This circuitry saves more power, but at internal reset in the FG2 device, the MTRC will be left active with
its last configured settings.
If MTVDD will be applied, the signal at MTRESET pin will release the reset mode of the MTRC. The
capacitor will cause a delay between MTVDD apply and MTRESET release, to ensure the minimum
specified time between this points of time.
If the FG2 will be reset via an internal (LVI or WD) or external function (RESET), the P port will be set
XX
into its reset mode (input) but the pull up resistor R will hold the MTRC in its normal operation mode.
PU
Therefore the last configured action (PWM signal) will remain. It has to be checked if this leads to criti-
cal application states.
After the RESET release of the FG2 device, the MTRC should be reset via MTRESET pin as soon as
possible (i.e. in the start-up code).
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Preliminary User's Manual U17763EE1V1UD00