Epson S1D13700 User's & Technical Manual page 96

Symbol
f BUS clock frequency
CLK
T BUS clock period
CLK
AB [16 : 0], WR# (R/W#) and CS# and AS# and RD# (UDS#, LDS#)
t1
setup to first CLK rising edge
t2 CS# and AS# asserted to WAIT# (DTACK#) driven
t3 RD# = 0 (UDS# = 0 or LDS# = 0) to DB [15 : 0] driven (read cycle)
t4 AB [16 : 0], WR# (R/W#) and CS# hold from AS# rising edge
t5 WAIT# (DTACK#) falling edge to RD# (UDS#, LDS#) rising edge
RD# (UDS#, LDS#) deasserted high to reasserted low
- When read
t6
- when Write (next cycle = write cycle)
- when Write (next cycle = read cycle)
t7 CLK rising edge to WAIT# (DTACK#) high impedance
t8 AS# rising edge to WAIT# (DTACK#) rising edge
DB [15 : 0] valid to 4th CLK rising edge where CS# = 0, AS# = 0 and
t9
either RD# = 0 (UDS# = 0 or LDS# = 0) (wirte cycle)
t10 DB [15 : 0] hold from RD# (UDS#, LDS#) falling edge (wirte cycle)
RD# (UDS#, LDS#) rising edge to DB [15 : 0] high impedance (read
t11
cycle)
DB [15 : 0] valid setup time to 2nd CLK falling edge after WAIT#
t12
(DTACK#) goes low (read cycle)
Cycle Length
t13
S1D13700 Technical Manual
Motorola M68K#1 Interface Timing
Parameter
Read
Write (next write cycle)
Write (next read cycle)
EPSON
5: SPECIFICATIONS
[V = 0V, V = 3.0 – 3.6V, Ta = -40 – 85°C]
SS DD
Spec
Min. Max.
— 64
1/f —
CLK
9 —
1 10
3Tclk+9ns —
0 —
1 —
1Tclk
—
2Tclk+8ns
5Tclk+8ns
— 1T
CLK
3 15
1 —
4 —
8 —
8 —
7
8 —
11
Unit
MHz
ns
ns
ns
ns
ns
T
CLK
ns
ns
ns
-2 ns
ns
T
CLK
ns
ns
ns
T
CLK
91