Epson S1D13700 User's & Technical Manual page 93

5: SPECIFICATIONS
Symbol
f BUS clock frequency
CLK
T BUS clock period
CLK
AB [16 : 0] setrup to first CLK rising edge where CS# = 0 and either
t1
RD# = 0 or WR# = 0
t2 CS# setup to CLK rising edge
t3 RD#, WR# setup to CLK rising edge
t4 RD#, WR# state change to WAIT# driven low
t5 RD# falling edge to DB [15 : 0] driven (ead cycle)
t6 DB [15 : 0] setup to 4th rising CLK edge after CS# = 0 and WR# = 0
t7 AB [16 : 0], CS# hold from RD#, WR# rising edge
CS# deasserted to reasserted
- When read
t8
- when Write (next cycle = write cycle)
- when Write (next cycle = read cycle)
t9 WAIT# rising edge to RD#, WR# rising edge
WR#, RD# deasserted to reasserted
- When read
t10
- when Write (next cycle = write cycle)
- when Write (next cycle = read cycle)
Rising edge of either RD# or WR# to WAIT# high impedance 0.5
t11
TCLK
t12 D [15 : 0] hold from WR# rising edge (write cycle)
t13 D [15 : 0] hold from RD# rising edge (read cycle)
Cycle Length
t14
88
Gemeric Bus Interface Timing
Parameter
Read
Write (next write cycle)
Write (next read cycle)
[V
SS
3Tc+11ns
2Tclk+10ns
5Tclk+10ns
2Tclk+10ns
5Tclk+10ns
EPSON
= 0V, V = 3.0 – 3.6V, Ta = -40 – 85°C]
DD
Spec
Min. Max.
— 64
1/f —
CLK
12 —
11 —
11 —
1 7
—
1 —
10 —
1Tclk
—
0 —
1Tclk
—
— 0.5
1 —
1 —
6
7 —
10
S1D13700 Technical Manual
Unit
MHz
ns
ns
ns
ns
ns
Tclk
T
CLK
ns
ns
ns
ns
ns
ns
ns
ns
T
CLK
ns
ns
T
CLK