Epson S1D13700 User's & Technical Manual page 21

3: COMMANDS AND COMMAND REGISTERS
Hard
Address Register name
Reset
r_P1_
0 x 8019 0 x 00
CGRAMAdr
r_P2_
1
0 x 00
0 x 801A *
CGRAMAdr
0 x 801B 0 x 00 r_P1_HdotScr
3
0 x 00 r_P1_CSRW
0 x 801C *
3
0 x 00 r_P2_CSRW
0 x 801D *
3
0 x 00 r_P1_CSRR
0 x 801E *
3
0 x 00 r_P2_CSRR
0 x 801F *
r_P1_
0 x 8020 0 x 00
GrayScale
*1 To ensure that two bytes are set at the same time, the low-order byte is fixed when the high-order byte is written.
*2 SLEEPIN = 0: Clock enable
Using the internal oscillator circuit causes the oscillator to start oscillating. Using an externally sourced
clock causes the clock to propagate to the internal circuits.
The internal timing circuit is released from reset status by writing to any register after setting SLEEPIN
= 0. (Therefore, internal SRAM cannot be accessed until that time.)
*3 CSRW: Write only (00h when read), CSRR: read only (write invalid).
Other registers can be written to or read from (in units of bits).
The following shows the relationship between memory and register maps in the S1D13700.
* The S1D13700 ignores any attempt to access address space 8030h–FFFFh. This address space may be employed as
a user area, but because there is no negate output available for the WAIT# pin of the S1D13700, inhibit access to this
address space when not in use.
16
bit7 bit6
SAGL SAGL
A7 A6
SAGH SAGH
A15 A14
0 0
CSRL CSRL
A7 A6
CSRH CSRH
A15 A14
CSRL CSRL
A7 A6
CSRH CSRH
A15 A14
0 0
(MSB DB7 – LSB DB0)
0000h
Display RAM
7FFFh
8000h
Register Area
0x8021 – 0x802F Reserve
802Fh
8030h
(CGROM Area)
85AFh
85B0h
Not Use
FFFFh
S1D13700 Memory Mapping (AB15 – AB0)
EPSON
bit5 bit4 bit3
SAGL SAGL SAGL
A5 A4 A3
SAGH SAGH SAGH
A13 A12 A11
0 0
CSRL CSRL CSRL
A5 A4 A3
CSRH CSRH CSRH
A13 A12 A11
CSRL CSRL CSRL
A5 A4 A3
CSRH CSRH CSRH
A13 A12 A11
0 0
Area
bit2 bit1
SAGL SAGL
A2 A1
SAGH SAGH
A10 A9
0 D2 D1
CSRL CSRL
A2 A1
CSRH CSRH
A10 A9
CSRL CSRL
A2 A1
CSRH CSRH
A10 A9
0 0 BPP1
S1D13700 Technical Manual
bit0
SAGL
A0
SAGH
A8
D0
CSRL
A0
CSRH
A8
CSRL
A0
CSRH
A8
BPP0