Video Proc. Board - Ikegami HTM-1550R Service Manual

2-3 VIDEO PROC. BOARD
(1) Outline
This board comprises the VIDEO block cirrui~ which adjusts the
gain, and background required for driving the CRT from the YPbPr
and RGB analog video inpul and which conlrols the beam feedback,
and the SYNC block circujt which generates HD and VD signals
from intema1 or external sync signa1s, and BLK signal from lhe de-
flection block FBT.
(2) Circuit description
(a)
VIDEO INPUT
The input buffer and amplifier (gain=2) the circuits are com-
posed in YpbPr, RGB and EXT SYNC each oulpul.
The Pr/Reh block is composed of TRll lo 14, Y/Gch block of
TR31 lo 34, Pb/Bch block of TR51 lo 54 and EXT SYNC block
ofTR71 lo 74.
(b) RGB
•
YPbPrMATRIX
The video signal circuit is a resistance matrix circuit for con-
verting RGB signals lo perform Y, Pb and Pr processing.
The Pr/Reh block is composed ofTRIOl lo 104, Y/Gch block of
TR301 lo 304, and Pb/Bch block ofTR501 lo 504.
ICI03, 1003 and IC503 are analog swilches for swilching RGB
lo YPbPr.
During !he Y, Pb, and Pr mode, as the circuit is set lo the H side,
signals from lhe TRlOl, 1R301 and TR501 emitters is selected.
During lhe RGB mode, as lhe circuit is set to the Lside, signals of
the circuit converted from RGB 10 YPbPr are selected.
(c) AUX VIDEO swilch
Cirruit, which rums on/off signals lo the YPbPr video bus lines.
The PNP+NPN emitter folJower circuil consisls of TR106/107,
TR306/308, and TR507/508.
The YPbPr signa1s are biased near the ground.
For 1hese signals, when AUX is nol selected (off), TR121, TR321
and TR521 become open.
As the cathode polential is higher than lhe DIOI, D302 and D501,
the video signal is cut off according to diode characteristics.
Furthermore, TR108, TR308 and TR508 are reverse-biased as the
video bus line is biased at approximately 0.7Y, and the video signa1
is cut off according lo diode characteristics of the transistor.
When AUX is selected (on), TR121, TR321 and TR521 are
short-circuited. As the cathode polential is ]ower than lhe D101,
D302 and D501, the video signal is supplied according 10 diode
characteristics.
The TRIOS, TR308 and TR508 are forward biased in order, and
video signal passes through each lransistor, and the video signal is
supplied to the video bus line.
Each option module is equipped with lhe same circuit, and the
same operatiofls are perfonned lo select the video signal
(d) VIDEO bus-line+ Isl CLAMP
The Y, Pb and Pr video signals including AUX signals are conneeled
lo various option modules via the MOTIIER BOARD.
The video level of this bus line is Y=l.28 Vp-p, Pb/Pr=±0.64 Vp-p.
The Pr/Reh block is composed of Ille TR!09/110 and TR122 lo
TR124, the Y/Gch block is composed of the TR309/fR310 and
TR322 lo TR324, and the Pb/Bch block is oomposed of the
TR509/TR110 and TR522 10 TR524.
The TR109/110, TR309/310 and TR509/510 are buffer amplifiers
composing gain=!.
TR122, TR322 and TR522 perform clamping lo delerrnine the DC
vollage for the blanking gale.
The Pb and Pr signal blocks differ from the back porch clamp of the
Y signal block as the sync chip is clamped.
(e) VIDEO delay+ BLK gale
To correct the aperture of the Y signal, each video signal (Y, Pb and
Pr) passes through DLIOI, DI.JOI and Dl.501.
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Only the Y signal is delayed here for aboul 30 ns.
It serves as a reference for the video signals hereafter.
The Pb and Pr signal blocks and Y signal block lo correct the phase
difference in the chroma circuit in the later stage change the delay
amount of parts.
Even during the deflection delay display, to d.isplay characters from
the MPU, the Y, Pb and Pr video signals are galed 10 the ground by
lhe BLK signal of the same phase in the horizontal direction using
analog swilches ICI05, IC305 and IC505.
DmingSET_UP, IC105, 1005 and IC505 are sel lo the Lside lo
ru1
all vjdeo signals.
During the MONO mode, ICIOS and IC505 aresel lo the I.side and
only the Y signal is supplied to the next stage.
(f) SUB
MATRIX
This is the gain=05 amplifier cirruil for correcting the R-Y and B-Y
level of the HDTV and SD1Y.
The Pr block is composed of the TR112 lo TRl14, the Y block is
composed of the TR312 lo TR314 and the Pb block is composed of
theTR5121oTR514.
During MATRIX on, the analog switch IC104 turns on to increac;e
the level ofonly the Pr block by 25%.
For the aperture signal, the analog swilch IC304 turns on only during
the HD1V mode, and is mixed
with
the video signal of the Yblock.
Only level conversion is performed for the Pb block.
The level of the video signals of this circuil is Y=0.35 Vp-p, Pb and
Pr=±0.\75 Vp-p.
(g)
VIDEO PROCESS
The video process consisls of chroma, aperture, contrast, brightn~
gain, and background control, and beam feedback moniloring. ·
All are processed by IC70I.
· The shadow function operates when the pu]se of the contrast control
is modula!ed.
As
the chroma level of !Cs differs belWeen the HDTV and SDTV
formats, when the chroma dala is 50% (referena:), lhe offset is cor-
reded by VR705 (HD1V) and VR706(SDTV).
The DC vollage (0 lo IOV) required for each oonlrol of!Cs is used
with oonverting the DC conlrol (0 lo 8V) from MPU using IC702 lo
IC706, and IC709.
The TST&CG_BLK pulse from the MPU is inpul lo Pin 16ofIC701,
and the high speed swilch in Ille IC is used lo swilch belWeen the Y, Pb
and Pr video signals and the character signal (RGB) from the MPU.
Controlling Pin 9 of JC701 lo low or_high sels lhe optimum matrix for
the conversion from the HDlV and SDlV formal YPbPr to RGB
(h) +6dBAMP
Cirruil, which amplifies the RGB video signal from IC701 lo the
level required by the amplifier in the lasl stage (gain=2).
The Reh block is composed ofTR115 lo TR119, the Gch block is
composed of TR315 to TR319 and the Bch block is oomposed of
TR515 lo TR519.
The DC vollage of the H.BLK is sampled by TR119, TR3!9 and
TR519, and the DC servo circuil consisting of IC106, 1006 and
JC506 oontrols the DC bias.
IC107, 1007 and IC507 lum on and off the R, G and B screens.
The beam feedback portion (RGB al the very lop of the screen) is
not turned off.
(i)APT
Composed of the TR701 lo TR705 for extracting edge signals from the
Y signal The edge signal is generated from the difference between
the Y signal with no delay and the Y signal delayed by 60 ns from
DI.JOI (30ns)
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DL701 (30ns).
After level conlrol in IC701, the edge signal is mixed with the Y sig-
nal delayed by 30 ns lo add the edge lo lhe signal.
The 12.5 MHz aperture correction can be perfonned in this circuit