Figure B-1. Ram5500 Block Diagram - Motorola MVME5500 Installation And Use Manual

RAM5500 Memory Expansion Module
B
Bank of 9 (x8)
Registers
AVC16722
B-2
mezzanine board design with two banks of memory. Each bank is 256MB
of ECC memory using 256Mb devices in 32MB x 8 device organization.
The RAM5500 provides a total added capacity of 512MB to the
MVME5500. The SDRAM memory is controlled by the GT-64260B,
which provides single-bit error correction and double-bit error detection.
ECC is calculated over 72-bits. The on-board I2C SROM contains SPD
data for the two banks, which is used by the memory controller for
configuration. Refer to the MVME5500 Single Board Computer
Programmer's Reference Guide (V5500A/PG) for more information.
The RAM5500 memory expansion module is connected to the host board
with a 140-pin AMP 4mm Free Height plug connector. This memory
expansion module draws +3.3V through this connector.
The RAM5500 SPD uses the SPD JEDEC standard definition and is
accessed at address $A2. Refer to the following section on SROM for more
details.
CLK (0:8)
SDRAM
Registers
AVC16374
A,
BA,
DQM
WE_L,
RAS_L,
CAS_L,
CS_C_L,
CS_D_L
MVME5500 Mezzanine Connector

Figure B-1. RAM5500 Block Diagram

SROM
PLL
SPD
Clock
Driver
SCL
CLK1
A1_SPD
SDA
A0_SPD
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