Cpu Cop Enable Header (J20); Pci Bus 0.0 Speed Header (J25) - Motorola MVME5500 Installation And Use Manual

Hardware Preparation and Installation
1

CPU COP Enable Header (J20)

PCI Bus 0.0 Speed Header (J25)

1-14
A 2-pin planar header enables the Riscwatch capability. No jumper
installed disables COP and enables boundary scan. A jumper across pins
1-2 enables the COP emulator debug.
1
2
Disables COP;
enables boundary scan
A 2-pin planar header that can force PCI bus 0.0 to run at 33 MHz rather
than the standard method of allowing the PMC board to control whether
the bus runs at 33 MHz or 66 MHz. No jumper installed allows the PMC
board to choose the PCI 0.0 bus speed. A jumper installed across pins 1-2
forces PCI bus 0.0 to run at 33 MHz.
J25
1
2
PMC board controls
PCI 0.0 bus speed
(factory configuration)
J20
1
2
Enables COP
emulator debug
(factory configuration)
1
2
Force PCI bus 0.0
to run at 33 MHz
J20
J25
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