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Interrupts
The LPC SERIRQ is used for interrupt interface to the Skylake SoC.
Each of the following devices can have an IRQ interrupt assigned to it and each with an interrupt
enable control for IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, and IRQ11:
8254 timers (with three interrupt status bits)
8x GPIOs (with one interrupt status bit per GPIO)16x Digital I/Os (with 1 interrupt status bit
per GPIO)
COM 1 UART (with 16550 interrupt status bits)
COM 2 UART (with 16550 interrupt status bits)
COM 3 UART (with the usual 16550 interrupt status bits).
COM 4 UART (with the usual 16550 interrupt status bits).
Watchdog timer (one status bit)
Common interrupts can be assigned to multiple devices if software can deal with it (this is
common on UARTs being handled by a common ISR).
Interrupt status bits for everything except the UARTs will "stick" and are cleared by a "write-
one" to a status register bit. The 16550 UART interrupts behave as defined for the 16550
registers and are a pass-through to the LPC SERIRQ.
Per the VersaAPI standard, anytime an interrupt on the SERIRQ is enabled, the slot becomes
active. All interrupts in the SERIRQ are high-true so when the slot becomes active, the slot will
be low when there is no interrupt and high when there is an interrupt.
FPGA I/O Space
The FPGA is mapped into I/O space on the LPC bus. The address range is mapped into a 64 byte
I/O window.
FPGA access: LPC I/O space
FPGA access size: All 8-bit byte accesses (16-bit like registers are aligned on 16-bit word
boundaries to make word access possible in software but the LPC bus still splits the accesses
into two 8-bit accesses)
FPGA address range: 0x1C80 to 0x1CBF (a 64-byte window)
The three 8254 timers only require four bytes of addressing and are located at the end of the
64-byte I/O block. The only requirement is that the base address must be aligned on a 4-byte
block. The table below lists the FPGA's I/O map.
EPU-4562 Programmer's Reference Manual
System Resources
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