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3.2.3.1 PCI Express interface signals
QuadMo747-x2000 can offer externally three PCI Express lane Gen 1.0a (2.5Gbps), which are managed by Intel
Here following the signals involved in PCI express management:
PCIE0_TX+/PCIE0_TX-: PCI Express lane #0, Transmitting Output Differential pair.
PCIE0_RX+/PCIE0_RX-: PCI Express lane #0, Receiving Input Differential pair.
PCIE1_TX+/PCIE1_TX-: PCI Express lane #1, Transmitting Output Differential pair.
PCIE1_RX+/PCIE1_RX-: PCI Express lane #1, Receiving Input Differential pair.
PCIE2_TX+/PCIE2_TX-: PCI Express lane #2, Transmitting Output Differential pair.
PCIE2_RX+/PCIE2_RX-: PCI Express lane #2, Receiving Input Differential pair.
PCIE_CLK_REF+/ PCIE_CLK_REF-: PCI Express Reference Clock, Differential Pair. Please consider that only one reference clock is supplied, while there are three
different PCI express lanes. When more than one PCI Express lane is used on the carrier board, then a zero-delay buffer must be used to replicate the reference
clock to all the devices.
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PCIE_WAKE#: Qseven
Module's Wake Input, it must be externally driven by devices requiring waking up the system. Since it is an Active-Low Input to the
module, this signal is pulled-up with a 1kΩ resistor to +3.3V_A power rail. On the carrier board, connect it directly to your PCI-e/miniPCI-e connector's WAKE#
signal, or to WAKE# signal of any eventual PCI-e Controller present on the Carrier Board.
PCIE_RST#: Reset Signal that is sent from Qseven
to drive externally a single RESET Signal. In case you need to supply Reset signal to multiple devices, you have to provide for a buffer on the carrier board.
QuadMo747-x2000
QuadMo747-x2000 User Manual - Rev. First Edition: 1.0 - Last Edition: 2.0 - Author: S.B. - Reviewed by G.G. Copyright © 2014 SECO S.r.l.
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Module to any PCI-e device available on the carrier board. It is a 3.3V active-low signal; it can be used directly
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NM10 Express Chipset.
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