Analog Devices ADSP-2181 Manual page 48

Connectors
Figure 3-3. JP2 Jumper Settings
• The
P2
These connectors can be used to access the ADSP-2181 processor's
signals for expansion or test purposes. For more information, see
"Expansion Port Connectors" on page
• The
U2
built, the board accepts a 27C512 (64K byte) or 27C010 (128K
byte) EPROM. Changing connections at
accept a 27C256 (32K byte), 27C020 (256K byte), 27C040 (512K
byte), or 27C080 (1 Mbyte) EPROM. This socket is connected to
the ADSP-2181 processor's byte-wide memory interface.
• The
R28
installed the ADSP-2181 processor can reset the board under soft-
ware control. The software would assert reset by configuring the
flag as an output and then setting it low.
PF0
• The
R29
tor is installed and X3 and C37 are removed, the codec can operate
off of the ADSP-2181 processor's
24.576 MHz clock. It is also necessary to change
quency value to stay within the codec's ratings.
3-6
and connectors are sites for 50-pin header connectors.
P3
socket is a socket for an EPROM in a DIP package. As
resistor is a site for a zero-ohm resistor. It this resistor is
resistor is another site for a zero-ohm resistor. If this resis-
ADSP-2181 EZ-KIT Lite Evaluation System Manual
3-7.
allows the board to
JP1
signal instead of its own
CLKOUT
X1
to a lower fre-