Power Supplies; Parallel Interface - Analog Devices EVAL-AD7492SDZ User Manual

EVAL-AD7492SDZ User Guide
Table 2. Link Options—Setup Condition
Link No. Position Function
LK1 A V
DRIVE
The CONVST signal is provided by the EVAL-SDP-CB1Z.
LK2 B
LK3 A The REFOUT pin of the
The RD signal is provided by the EVAL-SDP-CB1Z.
LK6 A
The CS signal is provided by the EVAL-SDP-CB1Z.
LK8 A
LK9 Inserted The buffered REF OUT voltage is divided by a factor of 3, and it is used as the bias input for U6.
LK10 B The V
LK14 B The AD7492
LK15 Inserted The unipolar V
LK20 A The buffered internal reference is used as the bias input for U6.
LK801 A It selects the VSS_−5V signal generated on the board as opposed to the externally connected VSS (J800-1) signal.
LK802 A It selects the VDD_+5V signal generated on the board as opposed to the externally connected VDD (J800-3) signal.
LK701 A It selects the AV

POWER SUPPLIES

Take care before applying power and signals to the evaluation
board to ensure that all link positions are as required by the
operating mode.
When using the EVAL-AD7492SDZ
EVAL-SDP-CB1Z board, connect the dc transformer to the J700
connector. AV , DV , and V
DD DD
supply is decoupled on the EVAL-AD7492SDZ
0.1 µF capacitors. A single ground plane is used on this board to
minimize the effect of high frequency noise interference.
Table 3. External Power Supply Required
Power
Supply Voltage
Terminal Range (V)
1
V +7 to +9
IN
V +5.5
DD
V −5.5
SS
2
AV +2.7 to +5.25
DD
V +2.7 to +5.25
DRIVE
1 When this is supplied, all other power supplies are available on-board. If this
supply is not used, all other supplies must be sourced from an external
source.
2 Analog supply voltage. This is the only supply voltage for all the analog
circuitry on the AD7492. The AV
DD
same potential and must not be more than 0.3 V apart, even on a transient
basis. Decouple this supply to AGND.
is set to AV .
DD
AD7492 is connected to the bias circuitry.
pin of AD7492 is connected to the buffered unipolar signal input that is applied to SK1.
IN
goes into partial sleep mode if low power operation is selected.
impedance matching resistor is connected into the circuit.
IN
signal generated on the board as opposed to being externally connected via J703.
DD
in conjunction with the
are generated on-board. Each
DRIVE
using 10 µF and
Purpose
Supplies all the on-board power
supplies that generate all the
required supplies to run the
evaluation board
Amplifier +VDD
Amplifier −VSS
ADC analog and digital supply
rails
Supply voltage for the output
drivers and digital input circuitry
and DV voltages should ideally be at the
DD

PARALLEL INTERFACE

The EVAL-AD7492SDZ
board using level shifters. The EVAL-SDP-CB1Zoperates at a
3.3 V logic level. This allows V
external CONVST signal can be supplied to the board via the SK2
SMB. Parallel data can only be monitored via the
board and software. A break out board
available that allows access to the digital lines.
Rev. 0 | Page 5 of 24
communicates with the EVAL-SDP-CB1Z
voltages to exceed 3.3 V. An
DRIVE
EVAL-SDP-CB1Z
ADZS-BRKOUT-EX3
UG-371
is