Evaluation Board Hardware; Device Description; Hardware Link Options - Analog Devices EVAL-AD7177-2SDZ User Manual

UG-849

EVALUATION BOARD HARDWARE

DEVICE DESCRIPTION

The AD7177-2 is a highly accurate, high resolution, multiplexed,
2-/4-channel (fully differential/single-ended) Σ-Δ ADC. The
AD7177-2 has a maximum channel-to-channel scan rate of
10 kSPS (100 µs) for fully settled data. The output data rates
range from 5 SPS to 10 kSPS. The device includes integrated rail-
to-rail analog input and reference input buffers, an integrated
precision 2.5 V reference, and an integrated oscillator.
See the AD7177-2 data sheet for complete specifications. Consult
the data sheet in conjunction with this user guide when using
the evaluation board. Full details for the
available at the SDP-B product page on the Analog Devices website.
Table 1. Default Link and Solder Link Options
Default
Link Option
LK1 A
LK2 B
LK3 to LK7 Not inserted
LK8 to LK12 Inserted
SL1 A
SL2 A
SL3 A
SL4 C
SL5 B
SL8 A
SL9 A
SL10 A
SL11 A
G16 Inserted
G32 Not inserted
G64 Not inserted
G128 Not inserted
R49 to R51 Inserted
EVAL-SDP-CB1Z
Description
Selects the voltage applied to the power supply sequencer circuit (U3); dependent on AVDD1. Place in
Position A if using 5 V AVDD1, or Position B if using 2.5 V AVDD1.
Selects the external power supply from Connector J3 (Position A) or Connector J5 (Position B).
Inserting these links sets up the on-board noise test prior to SL8 to SL11 to allow the inputs to the on-board
amplifiers, U8 and U9, to be shorted. In this mode, all inputs short to REFOUT.
Inserting these links sets up the on-board noise test close to the ADC analog inputs. In this mode, all inputs
short to REFOUT.
Sets the voltage applied to the AVDD2 pin. Operates using the AVDD1 supply (default). Position B sets the
AVDD2 voltage to 3.3 V supply from the
Selects between an external or on-board AVDD1 source. Supplies AVDD1 from the
Selects between an external or on-board AVSS source. Supplies AVSS from the
Connects AIN4 to: A4/J6 (Position A), REFOUT pin on the
Position B and Position C are used to simplify using a single-ended input source.
Selects between an external or on-board IOVDD source. Supplies IOVDD from the
(default). The evaluation board operates with a 3.3 V logic.
Routes A0 to: AIN0 pin on the
of 0.8× (Position C), or J10-1 (Position D).
Routes A2 to: AIN2 pin on the
(Position C).
Routes A3 to: AIN3 pin on the
(Position C).
Routes A1 to: AIN1 pin on the
of 0.8× (Position C), or J10-7 (Position D).
Sets the on-board In-amp (U8) to a gain of 16. Only one of G16, G32, G64, and G128 should be inserted at a time.
Sets the on-board In-amp (U8) to a gain of 32. Only one of G16, G32, G64, and G128 should be inserted at a time.
Sets the on-board In-amp (U8) to a gain of 64. Only one of G16, G32, G64, and G128 should be inserted at a time.
Sets the on-board In-amp (U8) to a gain of 128. Only one of G16, G32, G64, and G128 should be inserted at a time.
Connects AVSS and AGND for single-supply operation. To operate in split supply mode, remove these links.

HARDWARE LINK OPTIONS

See Table 1 for default link options. By default, the evaluation
board is configured to operate from the supplied 9 V ac-to-dc
adapter connected to connector J5. The 5 V supply required for
the AD7177-2
regulator (LDO). The ADP7118, with a 5 V output voltage,
receives its input voltage from J3 or J5 (depending on the
position of LK2) and generates a 5 V output.
are
ADP7118 (3.3 V) (U10) regulator.
AD7177-2
AD7177-2 (Position A), Buffer/In-amp U8 (Position B), Funnel Amp U9 with gain
AD7177-2 (Position A), Buffer U12 (Position B), or Funnel Amp U9 gain of 0.4×
AD7177-2 (Position A), Buffer U12 (Position B), or Funnel Amp U9 gain of 0.4×
AD7177-2 (Position A), Buffer/In-amp U8 (Position B), Funnel Amp U9 with gain
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EVAL-AD7177-2SDZ User Guide
comes from the ADP7118 on-board low dropout
ADP7118
ADP7182 (−2.5 V) (U4) (default).
(Position B), or AVSS (Position C).
ADP7118
(5 V) (U7) (default).
(3.3 V) (U10)