Serial Interface; Power Supplies - Analog Devices EVAL-AD7177-2SDZ User Manual

Evaluating the ad7177-2 32-bit, 10 ksps, sigma-delta adc with 100 µs settling and integrated analog input buffers
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UG-849

SERIAL INTERFACE

The
EVAL-AD7177-2SDZ
evaluation board connects via the
serial peripheral interface (SPI) to the Blackfin®
on the EVAL-SDP-CB1Z. There are four primary signals: CS ,
SCLK, and DIN (all inputs), and one output from the ADC,
DOUT/ RDY .
To operate the evaluation board in standalone mode, disconnect
the evaluation board from the SDP-B controller board. Use the
test points to connect the signals to an alternative digital capture
setup or the PMOD-compatible header (A7).
Table 3. Power Supply Configurations
Configuration
Input Voltage Range
Single Supply
7 V to 9 V
(Regulated)
Single Supply
7 V to 9 V, 5 V, and 3.3 V
(Unregulated)
Split Supply
7 V to 9 V
(Regulated)
Split Supply
7 V to 9 V, ±2.5 V, and 3.3 V
(Unregulated)
1
Only one configuration can be used at a time.
ADSP-BF527
1
Description
The 7 V to 9 V input is regulated to 5 V for AVDD1/AVDD2 and 3.3 V for IOVDD. This also
powers the external 5 V reference. See the Single Supply (Regulated) section in the Power
Supply Configurations section.
The input is unregulated and connects directly to AVDD1/AVDD2 and IOVDD from J5. The
7 V to 9 V input powers the external 5 V reference. See the Single Supply (Unregulated) section
in the Power Supply Configurations section.
The 7 V to 9 V input is regulated to 2.5 V for AVDD1/AVDD2, −2.5 V for AVSS and 3.3 V for
IOVDD. The 7 V to 9 V input powers the external 5 V reference. See the Split Supply
(Regulated) section in the Power Supply Configurations section.
The input is unregulated and connects directly to AVDD1/AVDD2 and IOVDD from J5. The
7 V to 9 V input powers the external 5 V reference. See the Split Supply (Unregulated) section in
the Power Supply Configurations section.
Rev. 0 | Page 6 of 14
EVAL-AD7177-2SDZ User Guide

POWER SUPPLIES

Power the evaluation board from the ac-to-dc adapter connected
to J5, or from an external bench top supply applied to J3 or J9.
Linear LDOs generate the required voltages from the applied
input voltage (V
) rail when using J3 or J5. Use J9 to bypass the
IN
on-board regulators. An
ADP7118
(single supply) and 2.5 V (split supply) supplies for the AVDD1
and AVDD2 rails to the ADC; a second
3.3 V for the IOVDD rail. The
SDP-B controller board as well as 5 V for the
converter to generate −5 V to supply the ADP7182. The
generates the −2.5 V supply for AVSS when operating in split
supply mode. Each supply is decoupled where it enters the board
and again at each device in accordance with the schematic.
Table 3 shows the various power supply configurations available,
including split supply operation.
regulator generates the 5 V
ADP7118
generates
ADP7104
supplies 5 V for the
ADM660
voltage
ADP7182

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