Ctr1 Clk Signal; Ctr1 Gate Signal; Ctr1 Out Signal - Measurement Computing PCI-DAS6031 User Manual

PCI-DAS6031 & PCI-DAS6033 User's Guide

CTR1 CLK signal

The CTR1 CLK signal can serve as the clock source for independent user counter 1. It can be selected through
software at the CTR1 CLK pin rather than using the on-board 10 MHz or 100 kHz sources. It is also polarity
programmable. The maximum input frequency is 10 MHz. There is no minimum frequency specified.
4-29 shows the timing requirements for the CTR1 CLK signal.

CTR1 GATE signal

You can use the CTR1 GATE signal for starting and stopping the counter, saving counter contents, etc. It is
polarity programmable and is available at the CTR1 GATE pin.
Figure 4-30 shows the minimum timing requirements for the CTR1 GATE signal.
Rising Edge Polarity
Falling Edge Polarity

CTR1 OUT signal

This signal is present on the CTR1 OUT pin. The CTR1 OUT signal is the output of one of the two user's
counters in an industry-standard 82C54 chip. For detailed information on counter operations, please refer to the
82C54 data sheet on our web site at www.mccdaq.com/PDFmanuals/82C54.pdf.
requirements for the CTR1 OUT signal for counter mode 0 and mode 2.
CTR1 CLK
CTR1 OUT (Mode 2)
CTR1 OUT (Mode 0)
t =100 ns minimum
p
t t
w-H w-L
t =15 ns minimum
w-H
t =25 ns minimum
w-L
Figure 4-29. CTR1 CLK signal timing
Figure 4-30. CTR1 GATE signal timing
Figure 4-31. CTR1 OUT signal timing
4-16
t
w
t = 25 ns minimum
w
TC
Functional Details
Figure
Figure 4-31 shows the timing