Measurement Computing PCI-DAS6031 User Manual page 20

PCI-DAS6031 & PCI-DAS6033 User's Guide
Except for the SYNC CLK signal, the DAQ-Sync timing and control signals are a subset of the AUXIO signals
available at the 100-pin I/O connector. These versions of the signals are used for board-to-board
synchronization and have the same timing specifications as their I/O connector counterparts. Refer to
signal timing" for explanations of signals and timing.
Use the SYNC CLCK signal to determine the master/slave configuration of a DAQ-Sync-enabled system. Each
system can have one master and up to four slaves. SYNC CLK is the 40 MHz time-base used to derive all board
timing and control. The master provides this clock to the slave boards so that all boards in the DAQ-Sync-
enabled system are timed from the same clock.
Analog In
64 CH S-E or
32 CH DIFF.
PCI-DAS6031
Only
A/D CONVERT
A/D START TRIGGER
A/D PACER GATE
A/D PACER OUT
SCANCLK
D/A START TRIGGER
D/A UPDATE
D/A PACER OUT
DIO (7:
EXT CTR1 CLK
CTR1 GATE
CTR1 OUT
CTR2 GATE
CTR2 OUT
THRESH-HI
12-BIT
THRESH-LO
12-BIT
Mux
ADC
&
16-BIT
Gain
DAC0
16-BIT
REF.
DAC1
16-BIT
DIO
0)
8-BIT
USER
COUNTER
82C54
1
Control
USER
COUNTER
2
Figure 4-1. Block diagram – PCI-DAS6031 and PCI-DAS6033
HOLDING
REGISTER
Queue
Buffer
16
D Q
EOC
MEMORY BUS
40 MHz
STC
SYSTEM
TIMING
&
CONTROL
CTR1 CLK
LOCAL BUS
Boot
EEPROM
PCI BUS (5V, 32-BIT, 33 MHZ)
4-3
Functional Details
DAC
ADC
Buffer
Buffer
(8K)
(16K)
(8K)
"DAQ