GE L60 Instruction Manual page 508

8.1 OVERVIEW
The logic of the transient blocking scheme is such that if a fault is detected (indicated by the operation of FDH) but no trip
takes place (as indicated by no output from the trip integrator timer) then AND3 produces an output to the transient blocking
timer (15-99)/(15-99). If this condition persists long enough for the transient blocking timer to produce an output, tripping is
blocked via the NOT input to AND4. This blocking of a trip output persists for the dropout time setting of the transient block-
ing timer after the AND3 output disappears as a result of FDH resetting or the trip integrator producing an output.
The pickup time delay setting of the transient blocking timer must be longer than the expected time difference between
FDH pickup and a trip integrator output during an internal fault. This insures no delay in tripping in the event of an internal
fault, as well as prolonged blocking during the clearing of an external fault during which transient power reversals may tend
to cause false tripping.
d) UNBLOCKING DUAL PHASE COMPARISON
The unblocking dual phase comparison scheme is a combination of a blocking scheme with permission to operate. This
scheme can be used with the FSK carrier only, as it requires monitoring of the check channel status before the fault using
the Guard (Low) frequency and during the fault by detecting/not detecting switching between Guard and Trip (High) fre-
quencies. If both Trip and Guard frequencies disappear prior the fault Guard frequency (i.e. during the fault), then the relay
is produces a trip within the programmable trip window time (typically 150 ms) after the FDH detector operates.
8
The above figure illustrates the state machine used for this scheme. The state machine is started when a fault is detected
by FDL. At this moment, the Guard frequency status (Rx1N) is checked. If the Guard frequency is absent, the scheme is
locked up, and 87PC is blocked until FDL resets.
If the Guard frequency is present upon fault occurrence, then a switch from Guard to Trip is expected during the next
15 ms. Once this occurs, the scheme is unblocked and regular dual phase comparison (on both positive and negative
halves of the sinewave) takes place. If both Guard and Trip frequencies are not present when the 15 ms timer expires, then
the phase comparison scheme is allowed to operate during the trip window time after FDH picks up.
Benefits of this scheme are that operating time is faster compared with single phase comparison with enough security built
into the scheme.
8-22
Yes
CH OK before FLT
Is Rx1P=1
(BLOCK 87PC=1)
Yes
No
FDL =0
CH Live
Unblocking
(BLOCK 87PC=0)
Figure 8–17: UNBLOCKING DUAL FREQUENCY PHASE COMPARISON
L60 Line Phase Comparison System
RESET
(BLOCK 87PC=0)
FDL=1
Is Rx1N=1
(BLOCK 87PC=1)
No
CH Fail before FLT
Is FDL=1
(BLOCK 87PC=1)
Timing
Timed out
Rx1N =1
Timed out
1cyc
Timed out
Rx1N =0
CH Fail
Trip Window
Timing
during FLT
(BLOCK 87PC=0)
8 THEORY OF OPERATION
No
Yes
Trip
window
831789A1.CDR
GE Multilin