Chipset Features Setup - Aaeon SBC-555 Manual

By choosing the CHIPSET FEATURES SETUP option from the
INITIAL SETUP SCREEN menu, the screen below is displayed.
The following configurations are based on the manufacturers
SETUP DEFAULTS settings.
R O M P C I / I S A B I O S ( 2 A 5 I I A K 9 )
C H I P S E T F E A T U R E S S E T U P
Auto Configuration
L2(WB) Tag Bit length
SRAM Back-to-Back
NA# Enable
Starting point of paging
Refresh Cycle Time (US)
RAS Pulse Width Refresh
RAS precharge Time
RAS to CAS Delay
CAS# Pulse Width (FP)
CAS# Pulse Width (ED0)
RAMW# Assertion Timing
CAS Precharge Time (FP)
CAS Precharge Time (EDO) : 1T/2T
Read Prefetch Memory RD
CPU to PCI Post Write
CPU to PCI Burse Mem. WR : Disabled
ISA Bus Clock Frequency
System BIOS Cacheable
This section allows you to configure the system based on the
specific features of the installed chipset. This chipset manages bus
speeds and access to system memory resources, such as DRAM
and the external cache. It also coordinates communications
between the conventional ISA bus and the PCI bus. It must be
stated that these items should never need to be altered. The default
settings have been chosen because they provide the best operating
conditions for your system.
The only time you might consider making any changes would be
if you discovered that data was being lost while using your system.
C M O S S E T U P U T I L I T Y
: Enabled
Video BIOS Cacheable
Memory Hole at 15M-16M
: 8 bits
: Enabled
: Disabled
: 1T
: 187.2
: 6T
: 4T
: 4T
: 2T
: 1T
: 3T
: 1T/2T
: Enabled
: 3T
: PCI CLK/4
: Enabled
Esc:Quit
F1 : Help
F5 : Old Values
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
: Enabled
: Disabled
: Select Item
PU/PD/+/- : Modify
(Shift)F2 : Color