Aaeon SBC-555 Manual page 45

Half-size 586 cpu card with pisa / isa bus
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Auto Configuration
Set this item to Enabled to pre-defined values for DRAM, cache..
timing according to CPU type & system clock. Thus, each item
value may display differently depending on your system configu-
rations.
When this item is enabled, the pre-difined items will become
SHOW-ONLY.
System BIOS Cacheable
When enabled, accesses to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller is
enabled.
Video BIOS Cacheable
As with caching the System BIOS above, enabling the Video
BIOS cache will cause access to video BIOS addressed at C0000H
to C7FFFH to be cached, if the cache controller is also enabled.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be
reserved for ISA cards. the memory must be mapped into the
memory space below 16 MB.

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