Basler A102K User Manual page 56

Operation and Features
With horizontal binning or full binning active, frame grabbers must take the state of
the data valid bit into account. And they often require the information that the hori-
zontal resolution is 696.
Changes to the Pixel Output with Horizontal Binning
Whenever horizontal binning or full binning is used, frame valid and line valid will rise at the normal
time. On the first pixel clock cycle, the averaged data for pixel number one is transmitted. On the
third pixel clock cycle, the averaged data for pixel number two is transmitted. On the fifth pixel
clock cycle, the averaged data for pixel number three is transmitted, and so forth. The data valid
bit is used to signal the even numbered pixel clock cycles as invalid.
As illustrated in Figure 3-18, the data for pixel number one is transmitted on the first pixel clock
cycle and data valid is high. On the second pixel clock cycle, valid data is not transmitted and the
data valid bit is low. On the third pixel clock cycle, data for pixel number two is transmitted and
data valid is high. On the fourth pixel clock cycle, valid data is not transmitted and the data valid
bit is low, and so forth.
Figure 3-18: Output Changes with Horizontal Binning
3-30
DRAFT
k
BASLER A102