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Enfora Enabler III-G
Modem Integration Guide
•
Full-duplex transmission
•
Programmable frame configuration
•
Continuous or burst transmission
•
Normal or alternate framing
•
Normal or inverted frame polarity
•
Short or long frame pulse
•
Programmable oversize frame length
•
Programmable frame length
•
Programmable interrupt occurrence time (TX and RX)
•
Error detection with interrupt generation on wrong frame length
GSM digital audio interface (DAI) operating modes (radio uplink, radio downlink, and
acoustics). The DAI mode is a GSM test interface that is used to determine the routing of
speech data for the devices being tested. In DAI mode, the MCSI is configured for direct
connection to the GSM system simulator interface, including the reset system simulator
(RSS) signal.
For hardware reference only. There is no generic firmware to support this function.
Firmware must be added to enable MCSI (TBD)
2
6.6.13. I
C (Pins 48, 50)
Pin Name
I2C_SCL
I2C_SDA
2
The multi-master I
C peripheral provides an interface between a local host (LH) such as an MPU
2
processor and any I
C -bus-compatible device that connects via the I
2
attached to the I
C bus can serially transmit/receive up to 8-bit data to/from the LH device through the
2
two-wire I
C interface.
2
This I
C peripheral supports any slave or master I
2
bus. The I
C controller supports the multi-master mode that allows more than one device capable of
controlling the bus to be connected to it. Each I
recognized by a unique address and can operate as either transmitter or receiver, according to the
function of the device. In addition to being a transmitter or receiver, a device connected to the I
can also be considered as master or slave when performing data transfers. Note that a master device is
the device which initiates a data transfer on the bus and generates the clock signals to permit that
transfer. During the transfer, any device addressed by this master is considered a slave.
or hardware reference only. There is no generic firmware to support this function.
F
Firmware must be added to enable I
2
I
C
Parameter/Conditions
VIH
High level input voltage
VIL
Low level input voltage
II
VOH
High level output voltage, IO = 3 mA
GSM0308PB001
Pin Number
Signal Direction
48
50
2
C (TBD)
Input leakage current
2
I/O
I
C interface Master serial clock
2
I/O
I
C interface Serial bi-directional data
2
C serial bus. External components
2
C -compatible device. The I
2
C device, including the on board processor, is
Min
1.26
0
1.44
Version DRAFT – 2/9/2007
45
Description
2
C bus is a multi-master
2
C bus
Typ
Max
1.8
1.9
0.54
±1
1.8
Units
V
V
μA
V
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