Figure 12 - External Power Control Signal (Using External Rc Circuit) - Enfora Enabler III-G Integration Manual

Enfora Enabler III-G
Modem Integration Guide
Figure 12 shows a variation of the connection in Figure 11 - External Power Control Signal (no external
processor) by using an external RC circuit to generate a pulse that will allow the processor to enter the
RTC deep sleep modes. This will keep the PWR_CTL_SIGNAL signal low for at least 500ms during
startup. To reset the module, power (BATT) must be cycled, and power must be removed long enough
for the RC to discharge.

Figure 12 - External Power Control Signal (using external RC circuit)

GSM0308PB001 Version DRAFT – 2/9/2007
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