Abi Test Limitations; Dma State Machine Test - HP Series 37 Reference Manual

Test Descriptions
• Inbound FIFO Test
• Passing Control Test
• Parity Error Test
• CRC Generation and Functions Test
.. ABI Interrupt Functions Test
• DMA Request Functions Test
ABI Test Limitations
Due to hardware limitations, the following functions of the ABI are NOT tested in this test section.
• ABI to HP-IB data paths - tested in the HP-IB Interface Drivers test section.
• Command parity error detection - tested on the ABI chip that has the programmable command
parity feature.
• Command parity error freeze - tested in the HP-IB Interface Drivers test section.
• Outbound data freeze - cannot be tested offline because it is only set when data enters the inbound
FIFO from the HP-IB, not from the outbound FIFO. This test is performed in the HP-IB Interface
Drivers test section.
• ABI Interrupt - tested in the Service Request (CSRQ) test section.
• ABI DMA request - tested in the DMA State Machine test section.
3.5 DMA STATE MACHINE TEST
This test section verifies the correct operation of the Direct Memory Address (DMA) state machine. Parts
of it use the diagnostic DMA clocking feature by utilizing the PIC's diagnostic hardware. This test section
verifies:
• The clocking and initialization of the DMA state machine.
• All transitions of the DMA state machine, including SIMB transactions. There are two main state
loops in the DMA state transition diagram: one for input DMA transfers, the other for output DMA
transfers. Each of these loops has two paths entering it from the initial state. Each also has two
normal termination exits and two abort termination exits. The tests are performed in the following
sequence: Can the initial state be asynchronously accessed? Can the four entry points to the transfer
loops be accessed? Do the loops function? Do the loops exit properly under normal termination
conditions? Does the channel service request sequence function properly?
• The outputs of each state.
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