Limitations; Operating Voltage; Nor Flash Memory Device; Table 12. Sram Chip Select Configuration - ST STM32L4R9I-EVAL User Manual

Hardware layout and configuration
.
Resistor
R134
9.20.1

Limitations

The SRAM addressable space is limited if some or all of A21 FMC address lines is shunted to
the CN12 connector for debug trace purposes. In such a case, the disconnected addressing
inputs of the SRAM device are pulled down by resistors.
the associated configuration elements.
9.20.2

Operating voltage

The SRAM device operating voltage is in the range from 2.4 V to 3.6 V.
9.21

NOR Flash memory device

M29W128GL70ZA6E, a 128-Mbit NOR Flash memory, 8 M x16 bit, is fitted on the
STM32L4R9I-EVAL main board, in U11 position. The STM32L4R9I-EVAL main board, as well
as the addressing capabilities of FMC, allow hosting M29W256GL70ZA6E, a 256-Mbit NOR
Flash memory device. This is the reason why the schematic diagram in
both devices.
The NOR Flash memory device is attached to the 16-bit data bus and accessed with FMC.
The base address is 0x6800 0000, corresponding to NOR/SRAM2 bank1. The NOR Flash
memory device is selected with FMC_NE3 chip select signal. 16-bit data word operation
mode is selected by a pull-up resistor connected to BYTE terminal of NOR Flash memory.
The jumper JP6 is dedicated for write protect configuration.
By default, the FMC_NWAIT signal is not routed to RB port of the NOR Flash memory device,
and, to know its ready status, its status register is polled by the demo software fitted in
STM32L4R9I-EVAL. This is modifiable with configuration elements, as shown in
Jumper
JP6
9.21.1 Limitations
The NOR Flash memory device's addressable space is limited if some or all of A21, A22 and
A23 FMC address lines are shunted to the CN12 connector for debug trace purposes. In such
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Table 12. SRAM chip select configuration

Fitting
Default setting.
In
SRAM chip select is controlled with FMC_NE1
SRAM is deselected. FMC_NE1 is freed for other application
Out
purposes.

Table 13. NOR Flash memory related jumper

Setting
Default setting.
NOR Flash memory write is enabled.
NOR Flash memory write is inhibited. Write protect is
activated.
DocID030791 Rev 2
Configuration
Section 9.4 provides information on
Figure 26
Configuration
UM2248
mentions
Table 13.