GE F60 Instruction Manual page 328

5.7 CONTROL ELEMENTS
Table 5–24: HI-Z SPECIFIC DATA
# NAME
0 EadCounts
1 ArcConfidence
2 AccumArcConf
3 RmsCurrent
4 HighROC
5 IOC
6 LossOfLoad
7 EadZeroed
8 HighZArmed
9 VoltageDip
10 HighEad
11 ArcBurst
12 VDisturbanceCc
13 VDisturbanceAbs
14 HarmonicRestraint
Table 5–25: HI-Z CAPTURE DATA
# NAME
5
1 StatusMask
2 AlgorithmState
3 EadZeroedFlag
4 SpectralFlag
5 ThreePhaseFlag
6 PhaseInfo[4]
The algorithm is in "Normal" state when it detects no abnormal activity on the power system. While in the "Normal" state,
any one of several power system events (a high output of the Expert Arc Detector, a significant loss of load, or a Hi-Z over-
current) cause the algorithm to move to the "Coordination Timeout" state, where it remains for the time specified by the
PROTECTION COORD TIMEOUT
detecting arcing or a downed conductor are:
1. the Expert Arc Detector Algorithm's output reaches a high level enough times, and
2. its high level was last reached when the algorithm's state was "Armed".
The "Arcing Sensitivity" setting determines what level constitutes a "high" output from the Expert Arc Detector Algorithm,
and the number that constitutes what "enough times" means. If these criteria are met, the algorithm temporarily moves to
either the "Arcing" state or the "Downed Conductor" state, the difference being determined by whether or not there was a
5-196
DESCRIPTION
Total number of EAD counts for the phase
ArcConfidence for the phase
Accumulated ArcConfidence for the phase
The 2-cycle RMS current for the phase
Flag indicating a high rate of change was detected
Flag indicating an instantaneous 2-cycle overcurrent was detected
Flag indicating a loss of load was detected
Flag indicating that this phase's EAD table was cleared
Flag indicating that this phase is armed for a high-Z detection
Flag indicating that a voltage dip was detected on this phase
Flag indicating that a high arc confidence occurred on this phase
Flag indicating that an arc burst was identified on this phase
Cycle-to-cycle voltage disturbance
Absolute voltage disturbance
Harmonic Restraint
DESCRIPTION
Bit-mask of the algorithm state (16 bits)
BIT_ARCING
BIT_DOWNED_COND
BIT_ARC_TREND
BIT_PHASE_A
BIT_PHASE_B
BIT_PHASE_C
BIT_PHASE_N
BIT_IOC_A
BIT_IOC_B
BIT_IOC_C
BIT_IOC_N
BIT_LOL_A
BIT_LOL_B
BIT_LOL_C
BIT_I_DISTURBANCE
BIT_V_DISTURBANCE
Present value of the High-Z output state machine: Normal = 0, Coordination Timeout = 1,
Armed = 2, Arcing = 5, Downed Conductor = 9
Flag indicating the EAD table was cleared
Flag indicating the Spectral algorithm has found a match
Flag indicating a three phase event was detected
Phase specific information for the three phase currents and the neutral (see table below)
setting. Following this interval, the algorithm moves into its "Armed" state. The criteria for
F60 Feeder Protection System
5 Z SETTINGS
OC
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