Intel 80C186EB Manual page 47

80C186EB 80C188EB 80L186EB 80L188EB
272433 –20
NOTE
The address driven is typically the location of the next instruction prefetch Under a majority of instruction sequences the
AD15 0 (AD7 0) bus will float while the A19 16 (A19 8) bus remains driven and all bus control signals are driven to their
inactive state
Pin names in parentheses apply to 80C188EB 80L188EB
Figure 19 Halt Cycle Waveforms
47