Intel 80C186EB Manual page 31

16-bit high-integration embedded processors
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AC SPECIFICATIONS
AC Characteristics 80C186EB20 80C186EB13
Symbol
SYNCHRONOUS INPUTS
T
TEST NMI INT4 0 BCLK1 0 T1 0IN
CHIS
READY CTS1 0 P2 6 P2 7
T
TEST NMI INT4 0 BCLK1 0 T1 0IN
CHIH
READY CTS1 0
T
AD15 0 (AD7 0) READY
CLIS
T
READY AD15 0 (AD7 0)
CLIH
T
HOLD PEREQ ERROR
CLIS
T
HOLD PEREQ ERROR
CLIH
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measure at V
for high time V
IH
3 Only required to guarantee I
CC
4 Specified for a 50 pF load see Figure 13 for capacitive derating information
5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF
6 See Figure 14 for rise and fall times
7 T
applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release
CHOV1
8 T
applies to RD and WR only after a HOLD release
CHOV2
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper operation
80C186EB 80C188EB 80L186EB 80L188EB
Parameter
for low time
IL
Maximum limits are bounded by T
(Continued)
20 MHz
13 MHz
Min
Max
Min
Max
10
10
3
3
10
10
3
3
10
10
3
3
T
and T
C
CH
CL
Units
Notes
ns
1 9
ns
1 9
ns
1 10
ns
1 10
ns
1 9
ns
1 9
31

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