Intel 80C186EB Manual page 9

16-bit high-integration embedded processors
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Table 2 Pin Description Nomenclature
Symbol
P
G
I
O
I O
S(E)
S(L)
A(E)
A(L)
H(1)
H(0)
H(Z)
H(Q)
H(X)
R(WH)
R(1)
R(0)
R(Z)
R(Q)
R(X)
I(1)
I(0)
I(Z)
I(Q)
I(X)
P(1)
P(0)
P(Z)
P(Q)
P(X)
80C186EB 80C188EB 80L186EB 80L188EB
Description
Power Pin (Apply
V
Voltage)
a
CC
Ground (Connect to V
)
SS
Input Only Pin
Output Only Pin
Input Output Pin
Synchronous Edge Sensitive
Synchronous Level Sensitive
Asynchronous Edge Sensitive
Asynchronous Level Sensitive
Output Driven to V
during Bus Hold
CC
Output Driven to V
during Bus Hold
SS
Output Floats during Bus Hold
Output Remains Active during Bus Hold
Output Retains Current State during Bus Hold
Output Weakly Held at V
CC
Output Driven to V
during Reset
CC
Output Driven to V
during Reset
SS
Output Floats during Reset
Output Remains Active during Reset
Output Retains Current State during Reset
Output Driven to V
during Idle Mode
CC
Output Driven to V
during Idle Mode
SS
Output Floats during Idle Mode
Output Remains Active during Idle Mode
Output Retains Current State during Idle Mode
Output Driven to V
during Powerdown Mode
CC
Output Driven to V
during Powerdown Mode
SS
Output Floats during Powerdown Mode
Output Remains Active during Powerdown Mode
Output Retains Current State during Powerdown Mode
during Reset
9

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