Intel 80C186EB Manual page 11

Pin Pin Input
Name Type Type
A18 16 I O A(L)
A19 ONCE
(A15 A8)
(A18 16)
(A19 ONCE)
S2 0 O
ALE O
BHE O
(RFSH)
RD O
WR O
READY I A(L)
S(L)
DEN O
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
80C186EB 80C188EB 80L186EB 80L188EB
Table 3 Pin Descriptions (Continued)
Output
States
H(Z) These pins provide multiplexed Address during the address
phase of the bus cycle Address bits 16 through 19 are presented
R(WH)
on these pins and can be latched using ALE These pins are
P(X)
driven to a logic 0 during the data phase of the bus cycle On the
80C188EB A15 – A8 provide valid address information for the
entire bus cycle During a processor reset (RESIN active) A19
ONCE is used to enable ONCE mode A18 16 must not be driven
low during reset or improper operation may result
H(Z) Bus cycle Status are encoded on these pins to provide bus
transaction information S2 0 are encoded as follows
R(Z)
P(1)
S2 S1 S0
0 0 0 Interrupt Acknowledge
0 0 1 Read I O
0 1 0 Write I O
0 1 1 Processor HALT
1 0 0 Queue Instruction Fetch
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive (no bus activity)
H(0) Address Latch Enable output is used to strobe address
information into a transparent type latch during the address phase
R(0)
of the bus cycle
P(0)
H(Z) Byte High Enable output to indicate that the bus cycle in progress
is transferring data over the upper half of the data bus BHE and
R(Z)
A0 have the following logical encoding
P(X)
A0 BHE Encoding (for the 80C186EB 80L186EB only)
0 0 Word Transfer
0 1 Even Byte Transfer
1 0 Odd Byte Transfer
1 1 Refresh Operation
On the 80C188EB 80L188EB RFSH is asserted low to indicate a
refresh bus cycle
H(Z) ReaD output signals that the accessed memory or I O device
must drive data information onto the data bus
R(Z)
P(1)
H(Z) WRite output signals that data available on the data bus are to be
written into the accessed memory or I O device
R(Z)
P(1)
READY input to signal the completion of a bus cycle READY
must be active to terminate any bus cycle unless it is ignored by
correctly programming the Chip-Select Unit
H(Z) Data ENable output to control the enable of bi-directional
transceivers in a buffered system DEN is active only when data is
R(Z)
to be transferred on the bus
P(1)
Description
Bus Cycle Initiated
11