Icc Versus Frequency And Voltage; Pdtmr Pin Delay Calculation - Intel 80C186EB Manual

I VERSUS FREQUENCY AND VOLTAGE
CC
The current (I ) consumption of the processor is
CC
essentially composed of two components I
I
CCS
I is the quiescent current that represents internal
PD
device leakage and is measured with all inputs or
floating outputs at GND or V
the device) I is equal to the Powerdown current
PD
and is typically less than 50 mA
I is the switching current used to charge and
CCS
discharge parasitic device capacitance when chang-
ing logic levels Since I
CCS
than I I can often be ignored when calculating
PD PD
I
CC
I is related to the voltage and frequency at which
CCS
the device is operating It is given by the formula
2 c
Power V I V
e e
c
I I I
e e e
CC CCS
Where V Device operating voltage (V
e
C Device capacitance
e
DEV
f Device operating frequency
e
I I Device current
e e
CCS CC
Measuring C on a device like the 80C186EB
DEV
would be difficult Instead C
the above formula by measuring I
and frequency (see Table 11) Using this C
ue I can be calculated at any voltage and fre-
CC
quency within the specified operating range
EXAMPLE Calculate the typical I
at 10 MHz 4 8V
I I 4 8 0 583
e e c
CC CCS
Parameter
C (Device in Reset)
DEV
C (Device in Idle)
DEV
1 Max C is calculated at
DEV
outputs loaded to 50 pF (including CLKOUT and OSCOUT)
2 Typical C
DEV
OSCOUT which are not loaded
and
PD
(no clock applied to
CC
is typically much greater
C f
DEV c
V C f
c DEV c
)
CC
is calculated using
DEV
at a known V
CC CC
val-
DEV
when operating
CC
10 28 mA
c
Table 11 Device Capacitance (C
Typ
0 583
0 408
40 C all floating outputs driven to V
b
is calculated at 25 C with all outputs loaded to 50 pF except CLKOUT and
80C186EB 80C188EB 80L186EB 80L188EB

PDTMR PIN DELAY CALCULATION

The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown A delay is required
only when using the on-chip oscillator to allow the
crystal or resonator circuit time to stabilize
NOTE
The PDTMR pin function does not apply when
RESIN is asserted (i e a device reset during Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabi-
lized)
To calculate the value of capacitor required to pro-
vide a desired delay use the equation
440 t C
c e
PD
Where t desired delay in seconds
e
C capacitive load on PDTMR in mi-
e
PD
crofarads
EXAMPLE To get a delay of 300 ms a capacitor
value of C 440 (300
e
c
PD
required Round up to standard (available) capaci-
tive values
NOTE
The above equation applies to delay times greater
than 10 ms and will compute the TYPICAL capaci-
tance needed to achieve the desired delay A delay
variance of 50% or 25% can occur due to
a b
temperature voltage and device process ex-
tremes In general higher V
perature will decrease delay time while lower V
and or higher temperature will increase delay time
) Values
DEV
Max Units
1 02 mA V MHz
0 682 mA V MHz
or GND and all
CC
(5V 25 C)
6
10 b ) 0 132 mF is
e
c
and or lower tem-
CC
CC
Notes
1 2
1 2
27