Agilent Technologies N6700 Series User Manual page 88

Status Subsystem
(IDENTICAL REGISTERS FOR EACH CHANNEL)
CONDITION
0
1
OV
1
2
OC
2
4
PF
3 8
CP+
4 16
OT
5 32
CP -
9
INH 512
10
UNR
1024
11
PROT
2048
STAT:QUES:COND?
STAT:QUES:PTR |:NTR <n>
STAT:QUES:PTR |:NTR ?
STANDARD EVENT
EVENT
0
OPC
1
2
QYE
4
3
DDE
8
4
EXE
16
5
CME 32
7
PON 128
*ESR?
(IDENTICAL REGISTERS FOR EACH CHANNEL)
CONDITION
0
1
CV
1
2
CC
2
4
OFF
3
WTG 8
meas
4
WTG 16
trans
STAT:OPER:COND?
STAT:OPER:PTR |:NTR <n>
STAT:OPER:PTR |:NTR ?
88
does a serial poll, RQS is cleared inside the register and returned in
bit position 6 of the response. The remaining bits of the Status Byte
register are not disturbed.
MAV Bit and Output Queue
The Output Queue is a first-in, first-out (FIFO) data register that
stores power system-to-controller messages until the controller reads
them. Whenever the queue holds one or more bytes, it sets the MAV
bit (4) of the Status Byte register.
QUESTIONABLE STATUS
PTR/NTR EVENT ENABLE
1 1 1
2 2
2
4 4
4
8 8 8
16 16 16
32 32 32
512
512 512
1024 1024 1024
2048 2048 2048
STAT:QUES:ENAB <n>
STAT:QUES:ENAB?
STAT:QUES:EVEN?
ERROR QUEUE
STATUS
ENABLE
1
SYST:ERR?
4
8
LOGICAL
OR
16
OUTPUT QUEUE
32
128
*ESE<n>
*ESE?
OPERATION STATUS
PTR/NTR EVENT ENABLE
1 1
1
2
2
2
4 4
4
8 8
8
16 16
16
STAT:OPER:ENAB <n>
STAT:OPER:ENAB?
STAT:OPER:EVEN?
CHAN 1
LOGICAL
OR
CHAN 2
SAME
CHAN 3
AS
CHAN 1
CHAN 4
Error
QUEUE
Error NOT
EMPTY
Error
QUES
OPER
Data
QUEUE
NOT
Data
EMPTY
Data
LOGICAL CHAN 1
OSUM
OR
OSUM
LOGICAL
CHAN 2
OR
OSUM
CHAN 3
SAME
AS
OSUM
CHAN 4
CHAN 1
QSUM
QSUM
LOGICAL
OR
QSUM
QSUM
SERVICE
REQUEST
STATUS BYTE ENABLE
ERR 2
4 4
3
8 8
4
MAV
16 16
ESB 5
32 32
MSS 6 RQS
64
7
128 128
*STB? *SRE<n>
*SRE?
SERVICE
REQUEST
GENERATION
Series N6700 User's Guide
LOGICAL
OR