Lapis ML610Q111 User Manual page 97

ML610Q111/ML610Q112 User's Manual
Chapter 7 Time Base Counter
HSCLK
HTBDR
HTBCLK
(8.192MHz)
1/n-Counter
8.192MHz to 512kHz
R
RESET
8
Data bus
HTBDR: High-speed time base counter frequency divide register
Figure 7-2 Configuration of High-Speed Time Base Counter
Note:
The frequency of HSCLK is changed by setting of SYSC1 bit and SYSC0 bit in the frequency control register 0 (FCON0).
FEUL610Q111 7-2