Lapis ML610Q111 User Manual page 289

• PB3MD1, PB3MD0 (bit 3)
The PB3MD1 and PB3MD0 bits are used to select the primary, secondary, tertiary and fourthly functions of the PB3 pin.
PB3MD1 PB3MD0
0 0
0 1
1 0
1 1
• PB4MD1, PB4MD0 (bit 4)
The PB4MD1 and PB4MD0 bits are used to select the primary, secondary, tertiary and fourthly functions of the PB4 pin.
PB4MD1 PB4MD0
0 0
0 1
1 0
1 1
• PB5MD1, PB5MD0 (bit 5)
The PB5MD1 and PB5MD0 bits are used to select the primary, secondary, tertiary and fourthly functions of the PB5 pin.
PB5MD1 PB5MD0
0 0
0 1
1 0
1 1
• PB6MD0, PB6MD0 (bit 6)
The PB6MD1 and PB6MD0 bits are used to select the primary, secondary tertiary and fourthly functions of the PB6 pin.
PB6MD1 PB6MD0
0 0
0 1
1 0
1 1
• PB7MD1, PB7MD0 (bit 7)
The PB7MD1 and PB7MD0 bits are used to select the primary, secondary, tertiary and fourthly functions of the PB7 pin.
PB7MD1 PB7MD0
0 0
0 1
1 0
1 1
Note:
If any bit combination out of the above is set to "Prohibited" and the corresponding bit of the Port B is specified to
output mode (selected in Port B control register), status of corresponding pin is fixed, regardless the contents of Port B
register (PBD)
High-impedance output mode: High-impedance
P-channel open drain output mode: High-impedance
N-channel open drain output mode: Fixed to "L"
CMOS output mode: High-impedance: Fixed to "L"
FEUL610Q111
General-purpose input/output mode (initial value)
SSIO data input
UART1 data output pin
Prohibited
General-purpose input/output mode (initial value)
SSIO data output
UART0 data output pin
UART1 data output pin
General-purpose input/output mode (initial value)
SSIO clock input/output
2
I C clock input/output
PWMF2 output
General-purpose input/output mode (initial value)
External clock (CLKIN) input
2
I C data input/output
PWMF1 output
General-purpose input/output mode (initial value)
Low-speed clock (LSCLK) output
PWMF0 output
PWMC output
ML610Q111/ML610Q112 User's Manual
Description
Description
Description
Description
Description
Chapter 16 Port B
16-10