Feul610Q111 - Lapis ML610Q111 User Manual

• Reset
−
Reset by the RESET_N pin
−
Reset by power-on
−
Reset by the watchdog timer (WDT) 2nd overflow
−
Reset by voltage level supervisor (VLS) function: Selectable by software
• Voltage level supervisor (VLS)
−
2ch
− Judgment accuracy: ±3.0% (Typ.)
−
The threshold voltages of VLS0 : (V
−
The threshold voltages of VLS1 (V
−
The VLS0 can be used as the low voltage level detector reset.
• Clock
−
Low-speed clock:
Built-in RC oscillation (32.768 kHz)
−
High-speed clock:
Built-in PLL oscillation (16.384 MHz), external clock(max. 8.192MHz)
* The clock of the CPU is 8.192MHz(max.)
−
Selection of high-speed clock mode by software:
Built-in PLL oscillation, external clock
• Power management
−
HALT mode : Instruction execution by CPU is suspended (peripheral circuits are in operating states).
−
STOP mode : Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits
are stopped.)
−
Clock gear : The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4 or 1/8 of the
oscillation clock)
−
Block Control Function : Power down (reset registers and stop clock supply) the circuits of unused peripherals.
• Shipment
−
ML610Q111 :
20-pin TSSOP
ML610Q111-xxxTD (Blank product: ML610Q111-NNNTD)
−
ML610Q112 :
32-pin LQFP
ML610Q112-xxxTC (Blank product: ML610Q112-NNNTC)
• Guaranteed operating range
− Operating ambient temperature: −40°C to 105°C (When the flash memory writing/erasing : −20°C to 85°C)
−
Operating voltage: V

FEUL610Q111

fall) : 2.85V (Typ. ) (V
DD
fall) : 4 types selectable 3.3V/ 3.6V/ 3.9V/ 4.2V (Typ.)
DD
= 2.7V to 5.5V
DD
ML610Q111/ML610Q112 User's Manual
rise) : 2.92V (Typ. )
DD
Chapter 1 Overview
1-3