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6.2.3 Frequency Control Register 1 (FCON1)
Address: 0F003H
Access: R/W
Access size: 8 bits
Initial value: 00H
7
FCON1
LPLL
R/W
R
Initial value
0
FCON1 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
[Description of Bits]
• SYSCLK (bit 0)
The SYSCLK bit is used to select system clock. It allows selection of the low-speed clock (LSCLK) or HSCLK
(1/nOSCLK: n = 1, 2, 4, 8) selected by using the high-speed clock frequency select bit (SYSC1, 0) of FCON0.
When the oscillation of high-speed clock is stopped (ENOSC bit = "0"), the SYSCLK bit is fixed to "0" and the
low-speed clock (LSCLK) is selected for system clock.
SYSCLK
0
LSCLK (initial value)
HSCLK
1
• ENOSC (bit 1)
The ENOSC bit is used to select enable/disable of the oscillation of the high-speed clock oscillator.
ENOSC
0
Disables high-speed oscillation (initial value)
1
Enables high-speed oscillation
• LPLL (bit 7)
The LPLL bit is used as a flag to indicate the oscillation state of PLL oscillation.
When the LPLL bit is set to "1", this indicates that the PLL oscillation is available. When the LPLL bit is set to "0", this
indicates that the PLL oscillation is inactive or the PLL oscillation is not available.
LPLL is a read-only bit.
LPLL
0
Disables the use of PLL oscillation (initial value)
Enables the use of PLL oscillation
1
Note:
− LPLL flag is a reference flag. The oscillation stabilization time for 3ms (max) is required after PLL oscillation starting.
− Although the oscillated frequency of PLL is 16.384MHz, a CPU clock is a maximum of 8.192MHz.
FEUL610Q111
6
5
4
0
0
0
Description
Description
Description
ML610Q111/ML610Q112 User's Manual
Chapter 6 Clock Generation Circuit
3
2
1
ENOSC
R/W
0
0
0
0
SYSCLK
R/W
0
6-4
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