Pwmd Counter Registers (Pwdch, Pwdcl) - Lapis ML610Q111 User Manual

10.2.11 PWMD Counter Registers (PWDCH, PWDCL)

Address: 0F924H
Access: R/W
Access size: 8/16 bits
Initial value: 00H
7
PWDCL PDC7
R/W R/W
Initial value 0
Address: 0F925H
Access: R/W
Access size: 8 bits
Initial value: 00H
7
PWDCH PDC15
R/W R/W
Initial value 0
PWDCL and PWDCH are special function registers (SFRs) that function as 16-bit binary counters.
When data is written to either PWDCL or PWDCH, PWDCL and PWDCH is set to "0000H". The data that is written is
meaningless. Write data while the PWM is stopped(PDSTAT, PDTGEN and PDRUN of PWDCON1 are "0").
When data is read from PWDCL, the value of PWDCH is latched. When reading PWDCH and PWDCL, use a word type
instruction or pre-read PWDCL.
The contents of PWDCH and PWDCL during PWM operation cannot be read depending on the combination of the PWM
clock and system clock. Table 10-2 shows PWDCH and PWDCL read enable/disable for each combination of the PWM
clock and system clock.
Table 10-2 PWDCH and PWDCL Read Enable/Disable during PWMD Operation
PWM clock
PDCK
LSCLK
LSCLK
HTBCLK
HTBCLK
PLLCLK
(16.384MHz)
FEUL610Q111
6 5
PDC6 PDC5
R/W R/W
0 0
6 5
PDC14 PDC13
R/W R/W
0 0
System clock
SYSCLK
LSCLK Read enabled
Read enabled. However, to prevent the reading of undefined
data during counting, read consecutively PWDCH or PWDCL
HSCLK
twice until the last data matched the previous data.
Read disabled
LSCLK
Read enabled
HSCLK
LSCLK
Read disabled
HSCLK
ML610Q111/ML610Q112 User's Manual
4 3
PDC4 PDC3 PDC2
R/W R/W
0 0
4 3
PDC12 PDC11 PDC10
R/W R/W
0 0
PWDCH and PWDCL read enable/disable
Chapter 10 PWM
2 1
PDC1 PDC0
R/W R/W R/W
0 0
2 1
PDC9 PDC8
R/W R/W R/W
0 0
0
0
0
0
10-14