Lapis ML610Q111 User Manual page 165

10.2.9 PWMD Period Registers (PWDPL, PWDPH)
Address: 0F920H
Access: R/W
Access size: 8/16 bits
Initial value: 0FFH
7
PWDPL PDP7
R/W R/W
Initial value 1
Address: 0F921H
Access: R/W
Access size: 8 bits
Initial value: 0FFH
7
PWDPH PDP15
R/W R/W
Initial value 1
PWDPH and PWDPL are special function registers (SFRs) to set the PWMD periods.
Note:
- When PWDPH or PWDPL is set to "0000H", the PWMD period buffer (PWDPBUF) is set to "0001H".
- The value written to PWDPH/PWDPL during PWMD stop (PDSTAT of PWDCON1 is "0") is transferred to PWDPBUF at
the same time. The value written to PWDPH/PWDPL during PWMD operation (PDSTAT of PWDCON1 is "1") is
transferred to PWDPBUF at the time of a start of the next period. For PWDPH and PWDPL updates during PWM
operation, see Section 10.3 "Description of Operation".
FEUL610Q111
6 5
PDP6 PDP5 PDP4
R/W R/W
1 1
6 5
PDP14 PDP13 PDP12
R/W R/W
1 1
ML610Q111/ML610Q112 User's Manual
4 3
PDP3 PDP2
R/W R/W R/W
1 1
4 3
PDP11 PDP10
R/W R/W R/W
1 1
Chapter 10 PWM
2 1 0
PDP1 PDP0
R/W R/W
1 1 1
2 1 0
PDP9 PDP8
R/W R/W
1 1 1
10-12