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6.2.2 Frequency Control Register 0 (FCON0)
Address: 0F002H
Access: R/W
Access size: 8/16 bits
Initial value: 3BH
7
FCON0
R/W
Initial value
0
FCON0 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
OSCM1 always returns the value "1".
[Description of Bits]
• SYSC1, SYSC0 (bits 1, 0)
The SYSC1 and SYSC0 bits are used to select the frequency of the high-speed clock (HSCLK) used for system clock and
peripheral circuits (including high-speed time base counter). OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can be
selected. The maximum operating frequency guaranteed for the system clock (SYSCLK) of this LSI is 8.192MHz.
At system reset, 1/8OSCLK is selected.
SYSC1
SYSC0
0
0
1
1
• OSCM0 (bits 2)
The OSCM0 bit is used to select the mode of the high-speed clock generation circuit. PLL oscillation mode, or external
clock input mode can be selected.
The setting of OSCM0 can be changed only when high-speed oscillation is being stopped (ENOSC bit of FCON1 is "0").
At system reset, PLL oscillation mode is selected.
OSCM0
0
Built-in PLL oscillation mode (initial value)
External clock input mode (PA2,PB6/CLKIN)
1
• OUTC1, OUTC0 (bits 5, 4)
The OUTC1 and OUTC0 bits are used to select the frequency of the high-speed output clock which is output when the
tertiary function of PA0 pin, PB0 pin are used.
OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can be selected.
At system reset, 1/8OSCLK is selected.
OUTC1
OUTC0
0
0
1
1
Note:
− To switch the mode of the high-speed clock generation circuit using the OSCM0 bit, stop the high-speed oscillation and
set the system clock to the low-speed clock (set the ENOSC bit and SYSCLK of FCON1 to "0").
− In external clock mode, an external clock is input from the PA2/CLKIN, PB6/CLKIN pin. And in external clock mode, input
a clock that does not exceed 8.192 MHz.
− In external clock mode, when using PA2/CLKIN and PB6/CLKIN as external clock input pin, PA2/CLKIN has the higher
priority.
FEUL610Q111
6
5
OUTC1
R/W
0
1
0
OSCLK
1
1/2OSCLK
1/4OSCLK
0
1
1/8OSCLK (initial value)
OSCLK
0
1
1/2 OSCLK
0
1/4 OSCLK
1/8 OSCLK (initial value)
1
ML610Q111/ML610Q112 User's Manual
4
3
OUTC0
OSCM1
OSCM0
R/W
R
1
1
Description
Description
Description
Chapter 6 Clock Generation Circuit
2
1
SYSC1
SYSC0
R/W
R/W
R/W
0
1
0
1
6-3
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