Lapis ML610Q112 Manuals

Manuals and User Guides for Lapis ML610Q112. We have 1 Lapis ML610Q112 manual available for free PDF download: User Manual

Lapis ML610Q112 User Manual (402 pages)

Brand: Lapis | Category: Semiconductors | Size: 3 MB

Table of Contents
5
Chapter 1 Overview

14
- Features
  15
- Configuration of Functional Blocks
  18
  - Block Diagram
    18
- Pins
  19
  - Pin Layout
    19
  - List of Pins
    20
  - Description of Pins
    22
  - Termination of Unused Pins
    25
Chapter 2 CPU and Memory Space

26
- Overview
  27
- Program Memory Space
  27
- Data Memory Space
  29
- Instruction Length
  31
- Data Type
  31
- Description of Registers
  32
  - List of Registers
    32
  - Data Segment Register (DSR)
    33
Chapter 3 Reset Function

34
- Overview
  35
  - Features
    35
  - Configuration
    35
  - List of Pin
    35
- Description of Registers
  36
  - List of Registers
    36
  - Reset Status Register (RSTAT)
    36
- Description of Operation
  37
  - Operation of System Reset Mode
    37
Chapter 4 MCU Control Function

38
- Overview
  39
  - Features
    39
  - Configuration
    39
- Description of Registers
  40
- Description of Operation
  48
Chapter 5 Interrupts (Ints)

53
Chapter 6 Clock Generation Circuit

81
Chapter 7 Time Base Counter

95
- Overview
  96
  - Features
    96
  - Configuration
    96
- Description of Registers
  98
- Description of Operation
  101
  - Low-Speed Time Base Counter
    101
  - High-Speed Time Base Counter
    102
Chapter 8 Timers

103
- Overview
  104
  - Features
    104
  - Configuration
    105
  - List of Pins
    107
- Description of Registers
  108
  - List of Registers
    108
  - Timer 8 Data Register (TM8D)
    109
  - Timer 9 Data Register (TM9D)
    110
  - Timer a Data Register (TMAD)
    111
  - Timer B Data Register (TMBD)
    112
  - Timer E Data Register (TMED)
    113
  - Timer F Data Register (TMFD)
    114
  - Timer 8 Counter Register (TM8C)
    115
  - Timer 9 Counter Register (TM9C)
    116
  - Timer a Counter Register (TMAC)
    117
  - Timer B Counter Register (TMBC)
    118
  - Timer E Counter Register (TMEC)
    119
  - Timer F Counter Register (TMFC)
    120
  - Timer 8 Control Register 0 (TM8CON0)
    121
  - Timer 9 Control Register 0 (TM9CON0)
    122
  - Timer a Control Register 0 (TMACON0)
    123
  - Timer B Control Register 0 (TMBCON0)
    124
  - Timer E Control Register 0 (TMECON0)
    125
  - Timer F Control Register 0 (TMFCON0)
    126
  - Timer 8 Control Register 1 (TM8CON1)
    127
  - Timer 9 Control Register 1 (TM9CON1)
    128
  - Timer a Control Register 1 (TMACON1)
    129
  - Timer B Control Register 1 (TMBCON1)
    130
  - Timer E Control Register 1 (TMECON1)
    131
  - Timer F Control Register 1 (TMFCON1)
    132
  - Timer E Control Register 2 (TMECON2)
    133
  - Timer F Control Register 2 (TMFCON2)
    134
  - Timer E Control Register 3 (TMECON3)
    136
  - Timer F Control Register 3 (TMFCON3)
    137
- Description of Operation
  138
  - Timer Basic Operation
    138
  - The External Timer Start/Stop Operation
    140
  - The External Timer Operation
    140
- Restriction of Timer
  142
  - Restriction 1
    142
  - Restriction 2
    142
- Specifying Port Registers
  143
  - Functioning PA0 (TM9OUT) as the Timer Output
    143
  - Functioning PC3 (TMFOUT) as the Timer Output
    144
Chapter 9 Watchdog Timer

145
- Overview
  146
  - Features
    146
  - Configuration
    146
- Description of Registers
  147
- Description of Operation
  150
  - Handling Example When You Do Not Want to Use the Watchdog Timer
    152
Chapter 10 PWM

153
- Overview
  154
  - Features
    154
  - Configuration
    155
  - List of Pins
    156
  - PWMC Period Registers (PWCPL, PWCPH)
    158
  - PWMC Duty Registers (PWCDL, PWCDH)
    159
  - PWMC Counter Registers (PWCCH, PWCCL)
    160
  - PWMC Control Register 0 (PWCCON0)
    161
  - PWMC Control Register 1 (PWCCON1)
    162
  - PWMC Control Register 2 (PWCCON2)
    163
  - PWMC Control Register 3 (PWCCON3)
    164
  - PWMD Duty Registers (PWDDL, PWDDH)
    166
  - PWMD Counter Registers (PWDCH, PWDCL)
    167
  - PWMD Control Register 0 (PWDCON0)
    168
  - PWMD Control Register 1 (PWDCON1)
    169
  - PWMD Control Register 2 (PWDCON2)
    170
  - PWMD Control Register 3 (PWDCON3)
    171
  - PWME Period Registers (PWEPL, PWEPH)
    172
  - PWME Duty Registers (PWEDL, PWEDH)
    173
  - PWME Counter Registers (PWECH, PWECL)
    174
  - PWME Control Register 0 (PWECON0)
    175
  - PWME Control Register 1 (PWECON1)
    176
  - PWME Control Register 2 (PWECON2)
    177
  - PWME Control Register 3 (PWECON3)
    178
  - PWMF Period Registers (PWFPL, PWFPH)
    179
  - PWMF0 Duty Registers (PWF0DL, PWF0DH)
    180
  - PWMF1 Duty Registers (PWF1DL, PWF1DH)
    181
  - PWMF2 Duty Registers (PWF2DL, PWF2DH)
    182
  - PWMF Counter Registers (PWFCH, PWFCL)
    183
  - PWMF Control Register 0 (PWFCON0)
    184
  - PWMF Control Register 1 (PWFCON1)
    185
  - PWMF Control Register 2 (PWFCON2)
    186
  - PWMF Control Register 3 (PWFCON3)
    187
  - PWMF Control Register 4 (PWFCON4)
    188
  - PWMF Control Register 5 (PWFCON5)
    189
- Description of Operation
  190
  - Start, Stop, and Clear Operations of PWM by External Input Control
    192
  - Emergency Stop Operation
    192
  - PWMF Operation
    193
  - Interrupt of PWM
    195
- Specifying Port Registers
  196
Chapter 11 Synchronous Serial Port

199
- Overview
  200
  - Features
    200
  - Configuration
    200
  - List of Pins
    201
- Description of Registers
  202
- Description of Operation
  207
  - Transmit Operation
    207
  - Receive Operation
    208
  - Transmit/Receive Operation
    209
- Specifying Port Registers
  210
  - Functioning as the SSIO Master Mode
    210
  - Functioning as the SSIO Slave Mode
    211
Chapter 12 UART

212
- Overview
  213
  - Features
    213
  - Configuration
    213
  - List of Pins
    214
- Description of Registers
  214
- Description of Operation
  225
  - Transfer Data Format
    225
  - Baud Rate
    226
  - Transmitted Data Direction
    227
  - Transmit Operation
    228
  - Receive Operation
    229
    
    Detection of Start Bit
    229
    
    Sampling Timing
    230
    
    Reception Margin
    231
- Specifying Port Registers
  232
Chapter 13 I2C Bus Interface Master

240
- Overview
  241
  - Features
    241
  - Configuration
    241
  - List of Pins
    241
- Overviewdescription of Registers
  242
- Description of Operation
  249
  - Communication Operating Mode
    249
    
    Start Condition
    249
    
    Repeated Start Condition
    249
    
    Slave Address Transmit Mode
    249
    
    Data Transmit Mode
    249
    
    Data Receive Mode
    249
    
    Control Register Setting Wait State
    249
    
    Stop Condition
    249
  - Communication Operation Timing
    250
  - Operation Waveforms
    252
- Specifying Port Registers
  253
  - Functioning PB5(SCL) and PB6(SDA) as the I2C
    253
Chapter 14 I2C Bus Interface Slave

254
- Overview
  255
  - Features
    255
  - Configuration
    255
  - List of Pins
    256
  - I2C Bus 1 Receive Register (I2C1RD)
    258
  - I2C Bus 1 Slave Address Register (I2C1SA)
    259
  - I2C Bus 1 Transmit Data Register (I2C1TD)
    260
  - I2C Bus 1 Control Register (I2C1CON)
    261
  - I2C Bus 1 Mode Register (I2C1MOD)
    262
  - I2C Bus 1 Status Register (I2C1STAT)
    263
- Description of Operation
  265
  - Communication Operating Mode
    265
    
    Start Condition
    265
    
    Slave Address Receive Mode
    265
    
    Communication Wait State
    265
    
    Data Transmit Mode
    265
    
    Data Receive Mode
    265
    
    Stop Condition
    265
  - Communication Operation Timing
    266
  - Operation Waveforms
    267
- Specifying Port Registers
  268
  - Functioning PB5(SCL) and PB6(SDA) as the I2C
    268
Chapter 15 Port a

269
- Overview
  270
  - Features
    270
  - Configuration
    271
  - List of Pins
    272
  - Port a Data Register (PAD)
    274
  - Port a Direction Register (PADIR)
    275
  - Port a Control Registers 0, 1 (PACON0, PACON1)
    276
  - Port a Mode Registers 0 (PAMOD0, PAMOD1))
    277
- Description of Operation
  278
Chapter 16 Port B

279
- Overview
  280
  - Features
    280
  - Configuration
    281
  - List of Pins
    282
- Description of Registers
  283
- Description of Operation
  290
Chapter 17 Port C

291
- Overview
  292
  - Features
    292
  - Configuration
    293
  - List of Pins
    294
  - Port C Data Register (PCD)
    296
  - Port C Direction Register (PCDIR)
    297
  - Port C Control Registers 0, 1 (PCCON0, PCCON1)
    298
  - Port C Mode Registers 0 (PCMOD0, PCMOD1)
    300
- Description of Operation
  302
Chapter 18 Port D

303
- Overview
  304
  - Features
    304
  - Configuration
    304
  - List of Pins
    305
  - Port D Data Register (PDD)
    307
  - Port D Direction Register (PDDIR)
    308
  - Port D Control Registers 0, 1 (PDCON0, PDCON1)
    309
- Description of Operation
  311
  - Input/Output Port Functions
    311
Chapter 19 Port AB Interrupts

312
- Overview
  313
  - Features
    313
  - Configuration
    313
- Description of Registers
  313
- Description of Operation
  316
  - Interrupt Request
    316
Chapter 20 Successive Approximation Type A/D Converter

317
- Overview
  318
  - Features
    318
  - Configuration
    318
- Description of Registers
  320
  - List of Registers
    320
  - SA-ADC Result Register 0L (SADR0L)
    321
  - SA-ADC Result Register 0H (SADR0H)
    321
  - SA-ADC Result Register 1L (SADR1L)
    322
  - SA-ADC Result Register 1H (SADR1H)
    322
  - SA-ADC Result Register 2L (SADR2L)
    323
  - SA-ADC Result Register 2H (SADR2H)
    323
  - SA-ADC Result Register 3L (SADR3L)
    324
  - SA-ADC Result Register 3H (SADR3H)
    324
  - SA-ADC Result Register 4L (SADR4L)
    325
  - SA-ADC Result Register 4H (SADR4H)
    325
  - SA-ADC Result Register 5L (SADR5L)
    326
  - SA-ADC Result Register 5H (SADR5H)
    326
  - SA-ADC Result Register 6L (SADR6L)
    327
  - SA-ADC Result Register 6H (SADR6H)
    327
  - SA-ADC Result Register 7L (SADR7L)
    328
  - SA-ADC Result Register 7H (SADR7H)
    328
  - SA-ADC Control Register 0 (SADCON0)
    329
  - SA-ADC Control Register 1 (SADCON1)
    330
  - SA-ADC Mode Register 0 (SADMOD0)
    331
- Description of Operation
  333
  - Settings of A/D Conversion Channels
    333
  - Operation of the Successive Approximation A/D Converter
    334
Chapter 21 Voltage Level Supervisor

335
- Overview
  336
  - Features
    336
  - Configuration
    336
- Description of Registers
  337
- Description of Operation
  341
  - Operation of Voltage Level Supervisor
    341
Chapter 22 Analog Comparator

342
- Overview
  343
  - Features
    343
  - Configuration
    343
  - List of Pins
    344
- Description of Registers
  344
- Description of Operation
  351
  - Comparator Functions
    351
  - Interrupt Request
    352
Chapter 23 Data Flash Memory

353
- Overview
  354
  - Features
    354
  - Flash Address Register (FLASHAL,H)
    356
  - Flash Data Register (FLASHDL,H)
    357
  - Flash Control Register (FLASHCON)
    358
  - Flash Accepter (FLASHACP)
    359
  - Flash Segment Register (FLASHSEG)
    360
  - Flash Self Register (FLASHSLF)
    360
  - Flash Protection Register (FLASHPRT)
    361
  - Flash Erase Abort Source Select Register (FLASHEAS)
    363
  - Flash Erase Status Register (FLASHEST)
    364
- Description of Operation
  365
  - Sector Erase Function
    366
  - Block Erase Function
    368
  - 1-Word Write Function
    370
  - Notes in Use
    372
Chapter 24 On-Chip Debug Function

374
- Overview
  374
- Method of Connecting to On-Chip Debug Emulator
  374
Appendix

376
Appendix A Registers

378
Appendix B Package

380
Appendix C Electrical

382
Appendix D Application Circuit Example

392
Appendix E Check List

394
- Revision History
  398

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Lapis ML610Q112 Manuals

Lapis ML610Q112 User Manual (402 pages)

Table of Contents

Chapter 1 Overview

Chapter 2 CPU and Memory Space

Chapter 3 Reset Function

Chapter 4 MCU Control Function

Chapter 5 Interrupts (Ints)

Chapter 6 Clock Generation Circuit

Chapter 7 Time Base Counter

Chapter 8 Timers

Chapter 9 Watchdog Timer

Chapter 10 PWM

Chapter 11 Synchronous Serial Port

Chapter 12 UART

Chapter 13 I2C Bus Interface Master

Chapter 14 I2C Bus Interface Slave

Chapter 15 Port a

Chapter 16 Port B

Chapter 17 Port C

Chapter 18 Port D

Chapter 19 Port AB Interrupts

Chapter 20 Successive Approximation Type A/D Converter

Chapter 21 Voltage Level Supervisor

Chapter 22 Analog Comparator

Chapter 23 Data Flash Memory

Chapter 24 On-Chip Debug Function

Appendix

Appendix A Registers

Appendix B Package

Appendix C Electrical

Appendix D Application Circuit Example

Appendix E Check List

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