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FEUL610Q111-05

ML610Q111/ML610Q112

User's Manual

Issue Date: Nov. 16, 2016

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Page 1 FEUL610Q111-05 ML610Q111/ML610Q112 User’s Manual Issue Date: Nov. 16, 2016...
Page 2: Feul610Q111
US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. 13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor. Copyright 2013-2016 LAPIS Semiconductor Co., Ltd.
Page 3: Feul610Q111
ML610Q111/ML610Q112 User’s Manual Preface This manual describes the operation of the hardware of the 8-bit microcontroller ML610Q111 / ML610Q112. The following manuals are also available. Read them as necessary.  nX-U8/100 Core Instruction Manual Description on the basic architecture and the each instruction of the nX-U8/100 Core ...
Page 4: Feul610Q111
ML610Q111/ML610Q112 User’s Manual Notation Classification Notation Description ♦ Numeric value xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F Indicates a binary number; “b” may be omitted. x: A value 0 or 1 ♦...
Page 5: Table Of Contents
ML610Q111/ML610Q112 User’s Manual Contents Contents Chapter 1 1 Overview ..............................1-1 Features ..............................1-1 Configuration of Functional Blocks ....................... 1-4 1.2.1 Block Diagram ..........................1-4 Pins ................................. 1-5 1.3.1 Pin Layout ............................ 1-5 1.3.2 List of Pins............................ 1-6 1.3.3 Description of Pins ........................1-8 1.3.4...
Page 6 ML610Q111/ML610Q112 User’s Manual Contents Chapter 5 5 Interrupts (INTs) ............................5-1 Overview ..............................5-1 5.1.1 Features ............................5-1 Description of Registers ......................... 5-2 5.2.1 List of Registers ..........................5-2 5.2.2 Interrupt Enable Register 0 (IE0) ....................5-3 5.2.3 Interrupt Enable Register 1 (IE1) ....................5-4 5.2.4...
Page 7 ML610Q111/ML610Q112 User’s Manual Contents 7.2.1 List of Registers ..........................7-3 7.2.2 Low-Speed Time Base Counter (LTBR) ..................7-4 7.2.3 High-Speed Time Base Counter Divide Register (HTBDR) ............7-5 Description of Operation ........................7-6 7.3.1 Low-Speed Time Base Counter ....................7-6 7.3.2...
Page 8 ML610Q111/ML610Q112 User’s Manual Contents 9.1.2 Configuration ..........................9-1 9.2 Description of Registers ......................... 9-2 9.2.1 List of Registers ..........................9-2 9.2.2 Watchdog Timer Control Register (WDTCON) ................9-3 9.2.3 Watchdog Timer Mode Register (WDTMOD) ................9-4 9.3 Description of Operation ........................9-5 9.3.1...
Page 9 ML610Q111/ML610Q112 User’s Manual Contents Chapter 11 11 Synchronous Serial Port ..........................11-1 11.1 Overview .............................. 11-1 11.1.1 Features ............................11-1 11.1.2 Configuration ..........................11-1 11.1.3 List of Pins..........................11-2 11.2 Description of Registers ........................11-3 11.2.1 List of Registers .......................... 11-3 11.2.2...
Page 10 ML610Q111/ML610Q112 User’s Manual Contents Chapter 13 13 I2C Bus Interface Master ........................... 13-1 13.1 Overview .............................. 13-1 13.1.1 Features ............................13-1 13.1.2 Configuration ..........................13-1 13.1.3 List of Pins..........................13-1 13.2 OverviewDescription of Registers ....................... 13-2 13.2.1 List of Registers .......................... 13-2 13.2.2...
Page 11 ML610Q111/ML610Q112 User’s Manual Contents 15.1.2 Configuration ..........................15-2 15.1.3 List of Pins..........................15-3 15.2 Description of Registers ........................15-4 15.2.1 List of Registers .......................... 15-4 15.2.2 Port A Data Register (PAD) ......................15-5 15.2.3 Port A Direction Register (PADIR) .................... 15-6 15.2.4...
Page 12 ML610Q111/ML610Q112 User’s Manual Contents 18.3 Description of Operation ........................18-8 18.3.1 Input/Output Port Functions ....................... 18-8 Chapter 19 19 Port AB Interrupts ............................19-1 19.1 Overview .............................. 19-1 19.1.1 Features ............................19-1 19.1.2 Configuration ..........................19-1 19.2 Description of Registers ........................19-1 19.2.1...
Page 13 ML610Q111/ML610Q112 User’s Manual Contents Chapter 22 22 Analog Comparator ........................... 22-1 22.1 Overview .............................. 22-1 22.1.1 Features ............................22-1 22.1.2 Configuration ..........................22-1 22.1.3 List of Pins..........................22-2 22.2 Description of Registers ........................22-2 22.2.1 List of Registers .......................... 22-2 22.2.2...
Page 14: Overview
Chapter 1 Overview...
Page 15: Features
ML610Q111/ML610Q112 User’s Manual Chapter 1 Overview 1 Overview Features This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as timers, PWM, UART, I C bus interface (master/slave), synchronous serial port, voltage level supervisor (VLS) function, and 10-bit successive approximation type A/D converter, are incorporated around 8-bit CPU nX-U8/100.
Page 16 Internal reference voltage : 0.1-0.8V (Selectable in 50mV increments) − Hysteresis (Comparator0 only): 20mV(Typ.) − Allows selection of with/without interrupt sampling and interrupt edge. • General-purpose ports (GPIO) − ML610Q111 : Input/output port × 15 channels − ML610Q112 : Input/output port × 25 channels FEUL610Q111...
Page 17: Feul610Q111
Block Control Function : Power down (reset registers and stop clock supply) the circuits of unused peripherals. • Shipment − ML610Q111 : 20-pin TSSOP ML610Q111-xxxTD (Blank product: ML610Q111-NNNTD) − ML610Q112 : 32-pin LQFP ML610Q112-xxxTC (Blank product: ML610Q112-NNNTC) • Guaranteed operating range −...
Page 18: Configuration Of Functional Blocks
PWMC* PWMD* AIN0 PWME* 10bit-ADC PWMF0* AIN5(AIN7) PWMF1* PWMF2* CMP0P Analog CMP0M PA0 to PA2 Comparator CMP0OUT* 8bit Timer PB0 to PB7 GPIO CMP1P PC0 to PC3 CMP1OUT* (PC4 to PC7) (PD0 to PD5) Figure 1-1 ML610Q111/ML610Q112 Block Diagram FEUL610Q111...
Page 19: Pins
ML610Q111/ML610Q112 User’s Manual Chapter 1 Overview Pins 1.3.1 Pin Layout Figure 1-2 show the TSSOP20 pin layout of the ML610Q111. PC1 / PWMF1 TM9OUT / PWMF0 / PC0 RESET_N PA0 / EXI0 / AIN0 / PWMC / OUTCLK / TM9OUT...
Page 20: List Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 1 Overview 1.3.2 List of Pins Table 1-1 shows list of pins. In the I/O column, “—” denotes a power supply pin, “I” an input pin, “O” an output pin, and “I/O” an input/output pin. Table 1-1 List of pins PIN No.
Page 21 ML610Q111/ML610Q112 User’s Manual Chapter 1 Overview PIN No. Primary function Secondary function Tertiary function quaternary function Descrip Descrip Descript Description LQFP TSSOP name name tion name tion name PWMF PWMF TM9O timer 9    Input/output port 0output output...
Page 22: Description Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 1 Overview 1.3.3 Description of Pins Table 1-2 shows description of pins. Table 1-2 (1/3) Description of pins Primary/ Secondary/ Pin name Description Logic Tertiary/ Quaternary System Reset input pin. When this pin is set to a “L” level, system reset mode is set and the internal section is initialized.
Page 23 ML610Q111/ML610Q112 User’s Manual Chapter 1 Overview Table 1-2 (2/3) Description of pins Primary/ Secondary/ Pin name Description Logic Tertiary/ Quaternary Timer TETG, External clock input pin used for both Timer E and Timer F. These pins Primary — TFTG are used as the primary function of the PA0-PA2, PB0-PB7 pins.
Page 24 ML610Q111/ML610Q112 User’s Manual Chapter 1 Overview Table 1-2 (3/3) Description of pins Primary/ Secondary/ Pin name Description Logic Tertiary/ Quaternary For testing I/O Input/output pin for testing. A pull-down resistor is internally connected. TEST — Positive Test pin for flash memory. A pull-down resistor is internally connected.
Page 25: Termination Of Unused Pins
ML610Q111/ML610Q112 User’s Manual Chapter 1 Overview 1.3.4 Termination of Unused Pins Table 1-3 shows methods of terminating the unused pins. Table 1-3 Termination of Unused Pins Recommended pin termination RESET_N Open TEST Open TESTF Open PA0 to PA2 Open PB0 to PB7...
Page 26: Cpu And Memory Space
Chapter 2 CPU and Memory Space...
Page 27: Overview
The vector table, which has 16-bit long data, can be used as reset vectors, hardware interrupt vectors, and software interrupt vectors. The unused software interrupt vector can use as a program code area. The program memory space consists of 1 segment and ML610Q111 has 24-Kbyte (12-Kword) capacity, ML610Q112 has 32-Kbyte (16-Kword) capacity.
Page 28 ML610Q111/ML610Q112 User’s Manual Chapter 2 CPU and Memory Space CSR:PC Segment 0 0:0000H Vector Table Area Program Code 0:00FFH ROM Window Area 0:0100H Program Code Area ROM Window Area 0:7FDFH 0:7FE0H Test Data Area 0:7FFFH 8bit Figure 2-2 Configuration of Program Memory Space of the ML610Q112 Notes: −...
Page 29: Data Memory Space
Data Memory Space The data memory space of this LSI consists of the ROM window area, 2-Kbyte RAM area(ML610Q111), 4-Kbyte RAM area(ML610Q112) and SFR area and 4-Kbyte Segment 2 of the data flash area and the ROM reference areas of the Segment 8 and the data flash reference areas of the Segment A.
Page 30 ML610Q111/ML610Q112 User’s Manual Chapter 2 CPU and Memory Space DSR: Data Segment 2 Segment 0 address DSR: Data address 2:0000H 0:0000H Data Flash Area ROM Window Area 2:0FFFH 2:1000H 0:5FFFH 0:6000H Unused Area 0:0DFFFH 0:0E000H Unused Area RAM Area 4 KB...
Page 31: Instruction Length
ML610Q111/ML610Q112 User’s Manual Chapter 2 CPU and Memory Space Instruction Length The length of an instruction is 16 bits. Data Type The data types supported include byte (8 bits) and word (16 bits). FEUL610Q111...
Page 32: Description Of Registers
ML610Q111/ML610Q112 User’s Manual Chapter 2 CPU and Memory Space Description of Registers 2.6.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F000H Data segment register FEUL610Q111...
Page 33: Data Segment Register (Dsr)
ML610Q111/ML610Q112 User’s Manual Chapter 2 CPU and Memory Space 2.6.2 Data Segment Register (DSR) Address: 0F000H Access: R/W Access size: 8 bits Initial value: 00H     DSR3 DSR2 DSR1 DSR0 Initial value DSR is a special function register (SFR) to retain a data segment address. For details of DSR, see “nX-U8/100 Core Instruction Manual”.
Page 34: Reset Function
Chapter 3 Reset Function...
Page 35: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 3 Reset Function 3 Reset Function Overview This LSI has the five reset functions shown below. If any of the five reset conditions is satisfied, this LSI enters system reset mode. • Reset by the RESET_N pin •...
Page 36: Description Of Registers
ML610Q111/ML610Q112 User’s Manual Chapter 3 Reset Function Description of Registers 3.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F001H Reset status register RSTAT Undefined 3.2.2 Reset Status Register (RSTAT) Address: 0F001H Access: R/W Access size: 8 bits Initial value: Undefined ―...
Page 37: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 3 Reset Function Description of Operation 3.3.1 Operation of System Reset Mode System reset has the highest priority among all the processing and any other processing being executed up to then is cancelled. The system reset mode is set by any of the following causes.
Page 38: Mcu Control Function
Chapter 4 MCU Control Function...
Page 39: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function 4 MCU Control Function Overview The operating states of this LSI are classified into the following 4 modes including system reset mode: • System reset mode • Program run mode • HALT mode •...
Page 40: Description Of Registers
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function Description of Registers 4.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F008H Stop code acceptor STPACP  0F009H Standby control register SBYCON  0F02AH Block control register 2 BLKCON2 ...
Page 41: Stop Code Acceptor (Stpacp)
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function 4.2.2 Stop Code Acceptor (STPACP) Address: 0F008H Access: W Access size: 8 bits Initial value:  (Undefined) STPACP Initial value STPACP is a write-only special function register (SFR) which enables for entering a STOP mode.
Page 42: Standby Control Register (Sbycon)
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function 4.2.3 Standby Control Register (SBYCON) Address: 0F009H Access: W Access size: 8 bits Initial value: 00H ― ― ― ― ― ― SBYCON ― ― ― ― ― ― Initial value SBYCON is a special function register (SFR) to control operating mode of MCU.
Page 43: Block Control Register 2 (Blkcon2)
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function 4.2.4 Block Control Register 2 (BLKCON2) Address: 0F02AH Access: R/W Access size: 8 bits Initial value: 00H    BLKCON2 DI2C0 DI2C1 DUA1 DUA0 DSIO0    Initial value BLKCON2 is a special function register (SFR) that controls the operation of the relevant block.
Page 44: Block Control Register 4 (Blkcon4)
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function 4.2.5 Block Control Register 4 (BLKCON4) Address: 0F02CH Access: R/W Access size: 8 bits Initial value: 00H        BLKCON4 DSAD      ...
Page 45: Block Control Register 6 (Blkcon6)
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function 4.2.6 Block Control Register 6 (BLKCON6) Address: 0F02EH Access: R/W Access size: 8 bits Initial value: 00H   BLKCON6 DTMF DTME DTMB DTMA DTM9 DTM8   Initial value BLKCON6 is a special function register (SFR) that controls the operation of the relevant block.
Page 46 ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function Note: − If the appropriate bit is set to “1” (operation disabled), the relevant block will be reset (all registers are initialized), and the clock of the relevant block will stop. When this bit is set to "1", the writing to all the registers of the relevant block will be invalid, an initial value is read when a register is read.
Page 47: Block Control Register 7 (Blkcon7)
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function 4.2.7 Block Control Register 7 (BLKCON7) Address: 0F02FH Access: R/W Access size: 8 bits Initial value: 00H     BLKCON7 DPWF DPWE DPWD DPWC     Initial value BLKCON7 is a special function register (SFR) that controls the operation of the relevant block.
Page 48: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function Description of Operation 4.3.1 Program Run Mode The program run mode is the state where the CPU executes instructions sequentially. At power-on reset, RESET_N pin reset, low level detection reset, VLS reset, or WDT overflow reset, the CPU executes instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after the system reset mode is released.
Page 49: Stop Mode
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function 4.3.3 STOP Mode The STOP mode is the state where low-speed oscillation and high-speed oscillation stop and the CPU and peripheral circuits stop the operation. When the entering the STOP mode is enabled by writing “5nH” (n: an arbitrary value) and “0AnH” (n: an arbitrary value) to the stop code acceptor (STPACP) sequentially and the STP bit of the standby control register (SBYCON) is set to “1”,...
Page 50: Stop Mode When Cpu Operates With High-Speed Clock
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function 4.3.3.2 STOP Mode When CPU Operates with High-Speed Clock When the CPU is operating with a high-speed clock and the STP bit of SBYCON is set to “1” with the entering the STOP mode enabled (by using the stop code acceptor(STPACP)), the STOP mode is entered and high-speed oscillation and low-speed oscillation stop.
Page 51: Note On Return Operation From Stop/Halt Mode
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function 4.3.3.3 Note on Return Operation from STOP/HALT Mode The operation of returning from the STOP mode and HALT mode varies according to the interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to IE7), and whether the interrupt is a non-maskable interrupt or a maskable interrupt.
Page 52: Block Control Function
ML610Q111/ML610Q112 User’s Manual Chapter 4 MCU Control Function 4.3.4 Block Control Function This LSI has a block control function, which resets and completely turns operating circuits of unused peripherals off to make even more reducing current consumption. When certain bits of block control registers are set to “1”, corresponding peripherals are reset (all registers are reset) and operating clocks for the peripherals stop.
Page 53: Interrupts (Ints)
Chapter 5 Interrupts (INTs)
Page 54: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5 Interrupts (INTs) Overview This LSI has 31 interrupt sources (External interrupts: 7 sources, Internal interrupts: 24 sources) and a software interrupt (SWI). For details of each interrupt, see the following chapters: Chapter 7, “Time Base Counter”...
Page 55: Description Of Registers
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) Description of Registers 5.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F010H Interrupt enable register 0  0F011H Interrupt enable register 1  0F012H Interrupt enable register 2 ...
Page 56: Interrupt Enable Register 0 (Ie0)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.2 Interrupt Enable Register 0 (IE0) Address: 0F010H Access: R/W Access size: 8 bits Initial value: 00H        EVLS        Initial value IE0 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 57: Interrupt Enable Register 1 (Ie1)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.3 Interrupt Enable Register 1 (IE1) Address: 0F011H Access: R/W Access size: 8 bits Initial value: 00H  EPB3 EPB2 EPB1 EPB0 EPA2 EPA1 EPA0  Initial value IE1 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 58 ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) • EPB2 (bit 6) EPB2 is the enable flag for the input/output port PB2 pin interrupt (PB2INT). EPB2 Description Disabled (initial value) Enabled • EPB3 (bit 7) EPB3 is the enable flag for the input/output port PB3 pin interrupt (PB3INT).
Page 59: Interrupt Enable Register 2 (Ie2)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.4 Interrupt Enable Register 2 (IE2) Address: 0F012H Access: R/W Access size: 8 bits Initial value: 00H     EI2CM EI2CS ESAD ESIO0     Initial value IE2 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 60: Interrupt Enable Register 3 (Ie3)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.5 Interrupt Enable Register 3 (IE3) Address: 0F013H Access: R/W Access size: 8 bits Initial value: 00H       ETM9 ETM8       Initial value IE3 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 61: Interrupt Enable Register 4 (Ie4)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.6 Interrupt Enable Register 4 (IE4) Address: 0F014H Access: R/W Access size: 8 bits Initial value: 00H     ECMP1 ECMP0 EUA1 EUA0     Initial value IE4 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 62: Interrupt Enable Register 5 (Ie5)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.7 Interrupt Enable Register 5 (IE5) Address: 0F015H Access: R/W Access size: 8 bits Initial value: 00H     ETMB ETMA ETMF ETME     Initial value IE5 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 63: Interrupt Enable Register 6 (Ie6)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.8 Interrupt Enable Register 6 (IE6) Address: 0F016H Access: R/W Access size: 8 bits Initial value: 00H   E32H E128H EPWF EPWE EPWD EPWC   Initial value IE6 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 64: Interrupt Enable Register 7 (Ie7)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.9 Interrupt Enable Register 7 (IE7) Address: 0F017H Access: R/W Access size: 8 bits Initial value: 00H       E16H       Initial value IE7 is a special function register (SFR) to control enable/disable for each interrupt request.
Page 65: Interrupt Request Register 0 (Irq0)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.10 Interrupt Request Register 0 (IRQ0) Address: 0F018H Access: R/W Access size: 8 bits Initial value: 00H       IRQ0 QVLS QWDT       Initial value IRQ0 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 66: Interrupt Request Register 1 (Irq1)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.11 Interrupt Request Register 1 (IRQ1) Address: 0F019H Access: R/W Access size: 8 bits Initial value: 00H  IRQ1 QPB3 QPB2 QPB1 QPB0 QPA2 QPA1 QPA0  Initial value IRQ1 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 67 ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) • QPB1 (bit 5) QPB1 is the request flag for the input port PB1 pin interrupt (PB1INT). QPB1 Description No request (initial value) Request • QPB2 (bit 6) QPB2 is the request flag for the input port PB2 pin interrupt (PB2INT).
Page 68: Interrupt Request Register 2 (Irq2)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.12 Interrupt Request Register 2 (IRQ2) Address: 0F01AH Access: R/W Access size: 8 bits Initial value: 00H     IRQ2 QI2CM QI2CS QSAD QSIO0     Initial value IRQ2 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 69: Interrupt Request Register 3 (Irq3)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.13 Interrupt Request Register 3 (IRQ3) Address: 0F01BH Access: R/W Access size: 8 bits Initial value: 00H       IRQ3 QTM9 QTM8       Initial value IRQ3 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 70: Interrupt Request Register 4 (Irq4)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.14 Interrupt Request Register 4 (IRQ4) Address: 0F01CH Access: R/W Access size: 8 bits Initial value: 00H     IRQ4 QCMP1 QCMP0 QUA1 QUA0     Initial value IRQ4 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 71: Interrupt Request Register 5 (Irq5)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.15 Interrupt Request Register 5 (IRQ5) Address: 0F01DH Access: R/W Access size: 8 bits Initial value: 00H     IRQ5 QTMB QTMA QTMF QTME     Initial value IRQ5 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 72: Interrupt Request Register 6 (Irq6)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.16 Interrupt Request Register 6 (IRQ6) Address: 0F01EH Access: R/W Access size: 8 bits Initial value: 00H   IRQ6 Q32H Q128H QPWF QPWE QPWD QPWC   Initial value IRQ6 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 73 ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) • Q32H (bit 7) Q32H is the request flag for the time base counter 32 Hz interrupt (T32HINT). Q32H Description No request (initial value) Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ6) or to the interrupt enable register (IE6), the interrupt shift cycle starts after the next 1 instruction is executed.
Page 74: Interrupt Request Register 7 (Irq7)
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.2.17 Interrupt Request Register 7 (IRQ7) Address: 0F01FH Access: R/W Access size: 8 bits Initial value: 00H       IRQ7 Q16H       Initial value IRQ7 is a special function register (SFR) to request an interrupt for each interrupt source.
Page 75: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) Description of Operation With the exception of the watchdog timer interrupt (WDTINT), interrupt enable/disable for 30 sources is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE0 to 7). WDTINT is non-maskable interrupts.
Page 76: Maskable Interrupt Processing
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.3.1 Maskable Interrupt Processing When an interrupt is generated with the MIE flag set to “1”, the following processing is executed by hardware and the processing of program shifts to the interrupt destination.
Page 77: Notes On Interrupt Routine
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.3.4 Notes on Interrupt Routine Notes are different in programming depending on whether a subroutine is called or not by the program in executing an interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or non-maskable.
Page 78 ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) A-2: When a subroutine is called by the program in executing an interrupt routine A-2-1: When multiple interrupts are disabled • Processing immediately after the start of interrupt routine execution Specify the “PUSH LR” instruction to save the subroutine return address in the stack.
Page 79 ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) State B: Non-maskable interrupt is being processed B-1: When a subroutine is not called • Processing immediately after the start of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to PC and those of the EPSW register to PSW.
Page 80: Interrupt Disable State
ML610Q111/ML610Q112 User’s Manual Chapter 5 Interrupts (INTs) 5.3.5 Interrupt Disable State Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is called an interrupt disabled state. See below for the interrupt disabled state and the handling of interrupts in this state.
Page 81: Clock Generation Circuit
Chapter 6 Clock Generation Circuit...
Page 82: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit 6 Clock Generation Circuit Overview The clock generation circuit generates and provides a low-speed clock (LSCLK), high-speed clock (HSCLK), built-in PLL clock (PLLCLK), high-speed oscillation clock (OSCLK), system clock (SYSCLK), low-speed output clock (LSCLK), and high-speed output clock (OUTCLK).
Page 83: List Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit 6.1.3 List of Pins Pin name Description High-speed clock output pin PA0/OUTCLK Used for the tertiary function of the PA0 pin High-speed clock output pin PB0/OUTCLK Used for the tertiary function of the PB0 pin...
Page 84 ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit 6.2.2 Frequency Control Register 0 (FCON0) Address: 0F002H Access: R/W Access size: 8/16 bits Initial value: 3BH   FCON0 OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0   Initial value FCON0 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
Page 85 ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit 6.2.3 Frequency Control Register 1 (FCON1) Address: 0F003H Access: R/W Access size: 8 bits Initial value: 00H      FCON1 LPLL ENOSC SYSCLK      Initial value FCON1 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
Page 86: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit Description of Operation 6.3.1 Low-Speed Clock 6.3.1.1 Low-Speed Clock Generation Circuit (built-in RC oscillating circuit) Figure 6-2 shows the circuit configuration of the low-speed clock generation circuit. The 32.768kHz RC oscillation clock generation circuit is activated by the occurrence of power ON reset or port reset or WDT reset or VLS reset.
Page 87: Operation Of Low-Speed Clock Generation Circuit
ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit 6.3.1.2 Operation of Low-Speed Clock Generation Circuit The low-speed clock generation circuit is activated by the occurrence of power-on reset. The low-speed clock (LSCLK) is supplied to the peripheral circuits after a lapse of the low-speed clock oscillation stabilization period (256 counts) after power-on.
Page 88: High-Speed Clock
ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2 High-Speed Clock For the high-speed clock generation circuit, built-in PLL oscillation mode or external clock input mode can be selected by the OSCM1 bit and OSCM0 bit of the frequecy control register0 (FCON0).
Page 89: High-Speed External Clock Input Mode
ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2.2 High-Speed External Clock Input Mode In high-speed external clock input mode, an external clock is input from the PA2 or PB6/CLKIN pin. When set as external clock input mode(OSCM0=”1”), supply of OSCLK is started after permitting an oscillation(ENOSC is set to "1.") and counting an external input clock 128 times.
Page 90: Operation Of High-Speed Clock Generation Circuit
ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2.3 Operation of High-Speed Clock Generation Circuit For the high-speed clock generation circuit, starting/stopping oscillation can be controlled by the frequency control register 0,1 (FCON0,1). After selecting high-speed oscillation mode and its frequency in FCON0, the oscillation will be started if the ENOSC bit of FCON1 is set to "1."...
Page 91: Switching Of System Clock
ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit 6.3.3 Switching of System Clock The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the frequency control registers (FCON0, FCON1). Figure 6-7 shows a flow of system clock switching processing (HSCLK→LSCLK) and Figure 6-8 shows a flow of system clock switching processing (LSCLK→HSCLK).
Page 92: Specifying Port Registers
ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit Specifying port registers For enable a clock output function, each related port register needs to be set up. Refer to the Chapter 15, “Port A” and the Chapter 16 “Port B” for details of each register.
Page 93: Functioning Pb0 (Outclk) As The High Speed Clock Output
ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit 6.4.2 Functioning PB0 (OUTCLK) as the High speed clock output Set PB0MD1 bit (bit0 of PBMOD1 register) to “1” for specifying the low speed clock output as the tertiary function of PB0.
Page 94: Functioning Pa2 (Clkin) As The External Clock Input
ML610Q111/ML610Q112 User’s Manual Chapter 6 Clock Generation Circuit 6.4.3 Functioning PA2 (CLKIN) as the External clock input Set PA2MD1 bit (bit2 of PAMOD1 register) to “1” as the tertiary function of PA2. Reg. name PAMOD1 register (Address: 0F255H)  ...
Page 95: Time Base Counter
Chapter 7 Time Base Counter...
Page 96: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 7 Time Base Counter 7 Time Base Counter Overview This LSI includes a low-speed time base counter (LTBC) and a high-speed time base counter (HTBC) that generate base clocks for peripheral circuits. By using the time base counter, it is possible to generate events periodically.
Page 97 ML610Q111/ML610Q112 User’s Manual Chapter 7 Time Base Counter HSCLK HTBDR HTBCLK (8.192MHz) 1/n-Counter 8.192MHz to 512kHz RESET Data bus HTBDR: High-speed time base counter frequency divide register Figure 7-2 Configuration of High-Speed Time Base Counter Note: The frequency of HSCLK is changed by setting of SYSC1 bit and SYSC0 bit in the frequency control register 0 (FCON0).
Page 98: Description Of Registers
ML610Q111/ML610Q112 User’s Manual Chapter 7 Time Base Counter Description of Registers 7.2.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value  Low-speed time base counter register 0F00AH LTBR High-speed time base counter  0F00BH HTBDR frequency divide register...
Page 99: Low-Speed Time Base Counter (Ltbr)
ML610Q111/ML610Q112 User’s Manual Chapter 7 Time Base Counter 7.2.2 Low-Speed Time Base Counter (LTBR) Address: 0F00AH Access: R/W Access size: 8 bits Initial value: 00H LTBR T1HZ T2HZ T4HZ T8HZ T16HZ T32HZ T64HZ T128HZ Initial value LTBR is a special function register (SFR) to read the T128HZ-T1HZ outputs of the low-speed time base counter.
Page 100: High-Speed Time Base Counter Divide Register (Htbdr)
ML610Q111/ML610Q112 User’s Manual Chapter 7 Time Base Counter 7.2.3 High-Speed Time Base Counter Divide Register (HTBDR) Address: 0F00BH Access: R/W Access size: 8 bits Initial value: 00H     HTBDR HTD3 HTD2 HTD1 HTD0    ...
Page 101: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 7 Time Base Counter Description of Operation 7.3.1 Low-Speed Time Base Counter The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset. The T128HZ, T32HZ, T16HZ, and T2HZ outputs of LTBC are used as interrupts and an interrupt is requested on the falling edge of each output.
Page 102: High-Speed Time Base Counter
ML610Q111/ML610Q112 User’s Manual Chapter 7 Time Base Counter 7.3.2 High-Speed Time Base Counter The high-speed time base counter is configured as a 4-bit 1/n counter (n = 1 to 16). In the 4-bit 1/n counter, the divided clock (1/16×HSCLK to 1/1×HSCLK) selected by the high-speed time base counter divide register (HTBDR) is generated as HTBCLK.
Page 103: Timers
Chapter 8 Timers...
Page 104: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8 Timers Overview This LSI includes 6 channels of 8-bit timers. 8.1.1 Features • The timer interrupt (TMnINT) is generated when the values of timer counter register (TMnC, n=8, 9, A, B, E, F) and timer data register (TMnD) coincide.
Page 105: Configuration
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.1.2 Configuration Figure 8-1 shows the configuration of the timers. TMnINT Matched Write TMnC PA0/TM9OUT Comparator PC0/TM9OUT TM9NEG LSCLK TMnCON0 TnCK HTBCLK TMnC TMnD TMnCON1 PLLCLK n=8,9,A,B Data bus (a) In 8-bit Timer Mode (Timers 8 to B)
Page 106 ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers TMnINT TMFNEG PA1/TMFOUT External Matched PC3/TMFOUT trigger Write TMnC (TnTG) Comparator TMnCON2 PA0 to PA2 CMP0 TMnCON3 PB0 to PB7 CMP1 TnCK LSCLK TMnC TMnD TMnCON0 HTBCLK TMnCON1 PLLCLK n=E,F Data bus (c) In 8-bit Timer Mode (Timer E, F)
Page 107: List Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.1.3 List of Pins Pin name Input/output Function External trigger input of timer E/F PA0/TnTG/TM9OUT Timer 9 output pin: Use for the quaternary function of PA0. External trigger input of timer E/F PA1/TnTG/TMFOUT Timer F output pin: Use for the quaternary function of PA1.
Page 108: Description Of Registers
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers Description of Registers 8.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F8E0H Timer 8 data register TM8D 8/16 0FFH TM8DC 0F8E1H Timer 8 counter register TM8C 0F8E2H Timer 8 control register 0...
Page 109: Timer 8 Data Register (Tm8D)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.2 Timer 8 Data Register (TM8D) Address: 0F8E0H Access: R/W Access size: 8/16 bits Initial value: 0FFH TM8D T8D7 T8D6 T8D5 T8D4 T8D3 T8D2 T8D1 T8D0 Initial value TM8D is a special function register (SFR) to set the value to be compared with the Timer 8 counter register (TM8C) value.
Page 110: Timer 9 Data Register (Tm9D)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.3 Timer 9 Data Register (TM9D) Address: 0F8E4H Access: R/W Access size: 8/16 bits Initial value: 0FFH TM9D T9D7 T9D6 T9D5 T9D4 T9D3 T9D2 T9D1 T9D0 Initial value TM9D is a special function register (SFR) to set the value to be compared with the value of the Timer 9 counter register (TM9C).
Page 111: Timer A Data Register (Tmad)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.4 Timer A Data Register (TMAD) Address: 0F8E8H Access: R/W Access size: 8/16 bits Initial value: 0FFH TMAD TAD7 TAD6 TAD5 TAD4 TAD3 TAD2 TAD1 TAD0 Initial value TMAD is a special function register (SFR) to set the value to be compared with the Timer A counter register (TMAC) value.
Page 112: Timer B Data Register (Tmbd)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.5 Timer B Data Register (TMBD) Address: 0F8ECH Access: R/W Access size: 8/16 bits Initial value: 0FFH TMBD TBD7 TBD6 TBD5 TBD4 TBD3 TBD2 TBD1 TBD0 Initial value TMBD is a special function register (SFR) to set the value to be compared with the value of the Timer B counter register (TMBC).
Page 113: Timer E Data Register (Tmed)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.6 Timer E Data Register (TMED) Address: 0F360H Access: R/W Access size: 8/16 bits Initial value: 0FFH TMED TED7 TED6 TED5 TED4 TED3 TED2 TED1 TED0 Initial value TMED is a special function register (SFR) to set the value to be compared with the Timer E counter register (TMEC) value.
Page 114: Timer F Data Register (Tmfd)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.7 Timer F Data Register (TMFD) Address: 0F368H Access: R/W Access size: 8/16 bits Initial value: 0FFH TMFD TFD7 TFD6 TFD5 TFD4 TFD3 TFD2 TFD1 TFD0 Initial value TMFD is a special function register (SFR) to set the value to be compared with the value of the Timer F counter register (TMFC).
Page 115: Timer 8 Counter Register (Tm8C)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.8 Timer 8 Counter Register (TM8C) Address: 0F8E1H Access: R/W Access size: 8 bits Initial value: 00H TM8C T8C7 T8C6 T8C5 T8C4 T8C3 T8C2 T8C1 T8C0 Initial value TM8C is a special function register (SFR) that functions as an 8-bit binary counter.
Page 116: Timer 9 Counter Register (Tm9C)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.9 Timer 9 Counter Register (TM9C) Address: 0F8E5H Access: R/W Access size: 8 bits Initial value: 00H TM9C T9C7 T9C6 T9C5 T9C4 T9C3 T9C2 T9C1 T9C0 Initial value TM9C is a special function register (SFR) that functions as an 8-bit binary counter.
Page 117: Timer A Counter Register (Tmac)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.10 Timer A Counter Register (TMAC) Address: 0F8E9H Access: R/W Access size: 8 bits Initial value: 00H TMAC TAC7 TAC6 TAC5 TAC4 TAC3 TAC2 TAC1 TAC0 Initial value TMAC is a special function register (SFR) that functions as an 8-bit binary counter.
Page 118: Timer B Counter Register (Tmbc)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.11 Timer B Counter Register (TMBC) Address: 0F8EDH Access: R/W Access size: 8 bits Initial value: 00H TMBC TBC7 TBC6 TBC5 TBC4 TBC3 TBC2 TBC1 TBC0 Initial value TMBC is a special function register (SFR) that functions as an 8-bit binary counter.
Page 119: Timer E Counter Register (Tmec)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.12 Timer E Counter Register (TMEC) Address: 0F361H Access: R/W Access size: 8 bits Initial value: 00H TMEC TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 Initial value TMEC is a special function register (SFR) that functions as an 8-bit binary counter.
Page 120: Timer F Counter Register (Tmfc)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.13 Timer F Counter Register (TMFC) Address: 0F369H Access: R/W Access size: 8 bits Initial value: 00H TMFC TFC7 TFC6 TFC5 TFC4 TFC3 TFC2 TFC1 TFC0 Initial value TMFC is a special function register (SFR) that functions as an 8-bit binary counter.
Page 121: Timer 8 Control Register 0 (Tm8Con0)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.14 Timer 8 Control Register 0 (TM8CON0) Address: 0F8E2H Access: R/W Access size: 8/16 bits Initial value: 00H    TM8CON0 T8OST T89M16 T8CS2 T8CS1 T8CS0    Initial value TM8CON0 is a special function (SFR) to control the Timer 8.
Page 122: Timer 9 Control Register 0 (Tm9Con0)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.15 Timer 9 Control Register 0 (TM9CON0) Address: 0F8E6H Access: R/W Access size: 8/16 bits Initial value: 00H    TM9CON0 T9OST T9NEG T9CS2 T9CS1 T9CS0    Initial value TM9CON0 is a special function (SFR) to control the Timer 9.
Page 123: Timer A Control Register 0 (Tmacon0)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.16 Timer A Control Register 0 (TMACON0) Address: 0F8EAH Access: R/W Access size: 8/16 bits Initial value: 00H    TMACON0 TAOST TABM16 TACS2 TACS1 TACS0    Initial value TMACON0 is a special function (SFR) to control the Timer A.
Page 124: Timer B Control Register 0 (Tmbcon0)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.17 Timer B Control Register 0 (TMBCON0) Address: 0F8EEH Access: R/W Access size: 8/16 bits Initial value: 00H     TMBCON0 TBOST TBCS2 TBCS1 TBCS0     Initial value TMBCON0 is a special function (SFR) to control the Timer B.
Page 125: Timer E Control Register 0 (Tmecon0)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.18 Timer E Control Register 0 (TMECON0) Address: 0F362H Access: R/W Access size: 8/16 bits Initial value: 00H     TMECON0 TECS2 TEFM16 TECS1 TECS0     Initial value TMECON0 is a special function (SFR) to control the Timer E.
Page 126: Timer F Control Register 0 (Tmfcon0)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.19 Timer F Control Register 0 (TMFCON0) Address: 0F36AH Access: R/W Access size: 8/16 bits Initial value: 00H      TMFCON0 TFCS2 TFCS1 TFCS0      Initial value TMFCON0 is a special function (SFR) to control the Timer F.
Page 127: Timer 8 Control Register 1 (Tm8Con1)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.20 Timer 8 Control Register 1 (TM8CON1) Address: 0F8E3H Access: R/W Access size: 8 bits Initial value: 00H       TM8CON1 T8STAT T8RUN       Initial value TM8CON1 is a special function register (SFR) to control the Timer 8.
Page 128: Timer 9 Control Register 1 (Tm9Con1)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.21 Timer 9 Control Register 1 (TM9CON1) Address: 0F8E7H Access: R/W Access size: 8 bits Initial value: 00H       TM9CON1 T9STAT T9RUN       Initial value TM9CON1 is a special function register (SFR) to control the Timer 9.
Page 129: Timer A Control Register 1 (Tmacon1)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.22 Timer A Control Register 1 (TMACON1) Address: 0F8EBH Access: R/W Access size: 8 bits Initial value: 00H       TMACON1 TASTAT TARUN       Initial value TMACON1 is a special function register (SFR) to control the Timer A.
Page 130: Timer B Control Register 1 (Tmbcon1)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.23 Timer B Control Register 1 (TMBCON1) Address: 0F8EFH Access: R/W Access size: 8 bits Initial value: 00H       TMBCON1 TBSTAT TBRUN       Initial value TMBCON1 is a special function register (SFR) to control the Timer B.
Page 131: Timer E Control Register 1 (Tmecon1)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.24 Timer E Control Register 1 (TMECON1) Address: 0F363H Access: R/W Access size: 8 bits Initial value: 00H      TMECON1 TESTAT TETGEN TERUN      Initial value TMECON1 is a special function register (SFR) to control the Timer E.
Page 132: Timer F Control Register 1 (Tmfcon1)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.25 Timer F Control Register 1 (TMFCON1) Address: 0F36BH Access: R/W Access size: 8 bits Initial value: 00H      TMFCON1 TFSTAT TFTGEN TFRUN      Initial value TMFCON1 is a special function register (SFR) to control the Timer F.
Page 133: Timer E Control Register 2 (Tmecon2)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.26 Timer E Control Register 2 (TMECON2) Address: 0F364H Access: R/W Access size: 8 bits Initial value: 00H    TMECON2 TEOST TETRM1 TETRM0 TEST1 TEST0    Initial value TMECON2 is a special function (SFR) to control the Timer E.
Page 134: Timer F Control Register 2 (Tmfcon2)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.27 Timer F Control Register 2 (TMFCON2) Address: 0F36CH Access: R/W Access size: 8 bits Initial value: 00H   TMFCON2 TFOST TFNEG TFTRM1 TFTRM0 TFST1 TFST0   Initial value TMFCON2 is a special function (SFR) to control the Timer F.
Page 135 ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers • TFOST (bit 7) The TFOST bit is used to select continuous mode/one shot mode of timer E. In cases where the 16-bit timer mode has been selected by setting TEFM16 of TMECON0 to “1”, the value of TFOST is invalid.
Page 136: Timer E Control Register 3 (Tmecon3)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.28 Timer E Control Register 3 (TMECON3) Address: 0F365H Access: R/W Access size: 8 bits Initial value: 00H     TMECON3 TESTSS TESTS2 TESTS1 TESTS0     Initial value TMECON3 is a special function register (SFR) to control the Timer E.
Page 137: Timer F Control Register 3 (Tmfcon3)
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.2.29 Timer F Control Register 3 (TMFCON3) Address: 0F36DH Access: R/W Access size: 8 bits Initial value: 00H     TMFCON3 TFSTSS TFSTS2 TFSTS1 TFSTS0     Initial value TMFCON3 is a special function register (SFR) to control the Timer F.
Page 138: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers Description of Operation 8.3.1 Timer basic operation When the TnRUN bit of timer 8 to B,E,F control register 1 (TMnCON1) is set to “1”, the timer counter (TMnC) is set to an operating state (TnSTAT is set to “1”) on the first falling edge of the timer clock (TnCK) being selected by the Timer 8 to B,E,F control register 0 (TMnCON0).
Page 139 ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers Figure 8-3 shows one shot mode operation timing of timer 8 to B, E, F. If timer out (TM9OUT and TMFOUT) is started with TnRUN of 1, timer out is inverted. Whenever the value of the count value of TMnC and the preset value of a timer n data register (TMnD) is matched , the output is returned to the initial value.
Page 140: The External Timer Start/Stop Operation
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.3.2 The external timer start/stop operation For the external timer start/stop operation of the timer E,F, the external timer start/stop is enabled when the external input is selected on timer control register 2(TMnCON2) and the timer control register 3(TMnCON3) and TnTGEN bit of timer control register 1(TMnCON1) is set as “1”.
Page 141 ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers TnCK PADn (external trigger input) TnRUN TnSTAT Write TMnC TMnC 87 88 5F 60 TMnD TMnINT (n=E,F) Figure 8-4(b) Continuous mode Operation Timing Diagram of Timer E,F ( timer count is started by the external input falling edge, timer count is stopped by the external input falling edge.
Page 142: Restriction Of Timer
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers Restriction of timer 8.4.1 Restriction 1 When using the 16bit timer configured cascading two 8bit timers, do not write “0FEh” to the lower byte of timer data register(TMnD, n=8, A, E). Set data to any value except for “0FEh”(“00h to 0FDh” or “0FFh”). There is no restriction for the higher byte of timer data register(TMmD, m=9, B, F).
Page 143: Specifying Port Registers
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers Specifying port registers For enable the timer output (TM9OUT, TMFOUT) function, each related port register needs to be set up. Refer to the Chapter 15, “Port A” , the Chapter 16 “Port B” and Chapter 17, “Port C” for details of each register.
Page 144: Functioning Pc3 (Tmfout) As The Timer Output
ML610Q111/ML610Q112 User’s Manual Chapter 8 Timers 8.5.2 Functioning PC3 (TMFOUT) as the timer output Set PC3MD1 bit (bit3 of PCMOD1 register) to “1” and PC7MD0 bit (bit3 of PCMOD0 register) to “1” for specifying the timer output as the quaternary function of PC3.
Page 145: Watchdog Timer
Chapter 9 Watchdog Timer...
Page 146: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 9 Watchdog Timer 9 Watchdog Timer 9.1 Overview This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in order to detect an undefined state of the MCU and return from that state.
Page 147: Description Of Registers
ML610Q111/ML610Q112 User’s Manual Chapter 9 Watchdog Timer 9.2 Description of Registers 9.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F00EH Watchdog timer control register WDTCON  0F00FH Watchdog timer mode register WDTMOD FEUL610Q111...
Page 148: Watchdog Timer Control Register (Wdtcon)
ML610Q111/ML610Q112 User’s Manual Chapter 9 Watchdog Timer 9.2.2 Watchdog Timer Control Register (WDTCON) Address: 0F00EH Access: R/W Access size: 8 bits Initial value: 00H WDTCON WDP/d0 Initial value WDTCON is a special function register (SFR) to clear the WDT counter.
Page 149: Watchdog Timer Mode Register (Wdtmod)
ML610Q111/ML610Q112 User’s Manual Chapter 9 Watchdog Timer 9.2.3 Watchdog Timer Mode Register (WDTMOD) Address: 0F00FH Access: R/W Access size: 8 bits Initial value: 02H      WDTMOD WDT2 WDT1 WDT0      Initial value WDTMOD is a special function register to set the overflow period of the watchdog timer.
Page 150: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 9 Watchdog Timer 9.3 Description of Operation The WDT counter starts counting by using a signal T256Hz of the low-speed time base counter, after the system reset has been released and the low-speed clock oscillation start.
Page 151 ML610Q111/ML610Q112 User’s Manual Chapter 9 Watchdog Timer Figure 9-2 shows an example of watchdog timer operation. Program Occurrence of start Low-speed abnormality oscillation start WDTMOD RESET_S WDTMOD setting setting System reset      Data: WDTCON Write WDTP...
Page 152: Handling Example When You Do Not Want To Use The Watchdog Timer
ML610Q111/ML610Q112 User’s Manual Chapter 9 Watchdog Timer 9.3.1 Handling example when you do not want to use the watchdog timer WDT counter is a free-run counter that starts count-up automatically after the system reset released and the low-speed clock (LSCLK) starts oscillating. If the WDT counter gets overflow, the WDT non-maskable interrupt occurs and then a system reset occurs.
Page 153: Pwm
Chapter 10...
Page 154: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10 PWM 10.1 Overview This LSI includes 4 channels of 16-bit PWM (Pulse Width Modulation). The PWM output (PWMC) function is assigned to the secondary function of the PA0(Port A) or the secondary function of the PB0(Port B) or the fourthly function of the PB7(Port B).
Page 155: Configuration
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.1.2 Configuration Figure 10 - 1 shows the configuration of the PWMC/PWMD/PWME and PWMF circuits. PnNEG PA0/PWMC PnFLG PB0/PWMC Write PWnCH PB7/PWMC Output control PWnINT External input Write PWnCL PA1/PWMD circuit (PnTG) PB1/PWMD Emergency stop...
Page 156: List Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.1.3 List of Pins Pin name Description PA0/ PnTG/ External trigger input PWMC output pin: Used for the secondary function of the PA0 pin. PWMC PA1/ PnTG/ External trigger input PWMD output pin: Used for the secondary function of the PA1 pin.
Page 157 ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2 Description of Registers 10.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F910H PWMC period register L PWCPL 8/16 0FFH PWCP PWMC period register H 0F911H PWCPH 0FFH 0F912H...
Page 158: Pwmc Period Registers (Pwcpl, Pwcph)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.2 PWMC Period Registers (PWCPL, PWCPH) Address: 0F910H Access: R/W Access size: 8/16 bits Initial value: 0FFH PWCPL PCP7 PCP6 PCP5 PCP4 PCP3 PCP2 PCP1 PCP0 Initial value Address: 0F911H Access: R/W Access size: 8 bits...
Page 159: Pwmc Duty Registers (Pwcdl, Pwcdh)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.3 PWMC Duty Registers (PWCDL, PWCDH) Address: 0F912H Access: R/W Access size: 8/16 bits Initial value: 00H PWCDL PCD7 PCD6 PCD5 PCD4 PCD3 PCD2 PCD1 PCD0 Initial value Address: 0F913H Access: R/W Access size: 8 bits...
Page 160: Pwmc Counter Registers (Pwcch, Pwccl)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.4 PWMC Counter Registers (PWCCH, PWCCL) Address: 0F914H Access: R/W Access size: 8/16 bits Initial value: 00H PWCCL PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 Initial value Address: 0F915H Access: R/W Access size: 8 bits...
Page 161: Pwmc Control Register 0 (Pwccon0)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.5 PWMC Control Register 0 (PWCCON0) Address: 0F916H Access: R/W Access size: 8/16 bits Initial value: 00H   PWCCON0 PCSDN PCNEG PCIS1 PCIS0 PCCS1 PCCS0   Initial value PWCCON0 is a special function register (SFR) to control PWMC.
Page 162: Pwmc Control Register 1 (Pwccon1)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.6 PWMC Control Register 1 (PWCCON1) Address: 0F917H Access: R/W Access size: 8 bits Initial value: 00H    PWCCON1 PCSTAT PCFLG PCSDST PCTGEN PCRUN    Initial value PWCCON1 is a special function register (SFR) to control PWMC.
Page 163: Pwmc Control Register 2 (Pwccon2)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.7 PWMC Control Register 2 (PWCCON2) Address: 0F918H Access: R/W Access size: 8/16 bits Initial value: 00H   PWCCON2 PCOST PCTRM1 PCTRM0 PCEXCL PCST1 PCST0   Initial value PWCCON2 is a special function register (SFR) to control PWMC.
Page 164: Pwmc Control Register 3 (Pwccon3)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.8 PWMC Control Register 3 (PWCCON3) Address: 0F919H Access: R/W Access size: 8 bits Initial value: 00H   PWCCON3 PCSDE1 PCSDE0 PCSTSS PCSTS2 PCSTS1 PCSTS0   Initial value PWCCON3 is a special function register (SFR) to control PWMC.
Page 165 ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.9 PWMD Period Registers (PWDPL, PWDPH) Address: 0F920H Access: R/W Access size: 8/16 bits Initial value: 0FFH PWDPL PDP7 PDP6 PDP5 PDP4 PDP3 PDP2 PDP1 PDP0 Initial value Address: 0F921H Access: R/W Access size: 8 bits...
Page 166: Pwmd Duty Registers (Pwddl, Pwddh)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.10 PWMD Duty Registers (PWDDL, PWDDH) Address: 0F922H Access: R/W Access size: 8/16 bits Initial value: 00H PWDDL PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 Initial value Address: 0F923H Access: R/W Access size: 8 bits...
Page 167: Pwmd Counter Registers (Pwdch, Pwdcl)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.11 PWMD Counter Registers (PWDCH, PWDCL) Address: 0F924H Access: R/W Access size: 8/16 bits Initial value: 00H PWDCL PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 Initial value Address: 0F925H Access: R/W Access size: 8 bits...
Page 168: Pwmd Control Register 0 (Pwdcon0)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.12 PWMD Control Register 0 (PWDCON0) Address: 0F926H Access: R/W Access size: 8/16 bits Initial value: 00H   PWDCON0 PDSDN PDNEG PDIS1 PDIS0 PDCS1 PDCS0   Initial value PWDCON0 is a special function register (SFR) to control PWMD.
Page 169: Pwmd Control Register 1 (Pwdcon1)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.13 PWMD Control Register 1 (PWDCON1) Address: 0F927H Access: R/W Access size: 8 bits Initial value: 00H    PWDCON1 PDSTAT PDFLG PDSDST PDTGEN PDRUN    Initial value PWDCON1 is a special function register (SFR) to control PWMD.
Page 170: Pwmd Control Register 2 (Pwdcon2)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.14 PWMD Control Register 2 (PWDCON2) Address: 0F928H Access: R/W Access size: 8/16 bits Initial value: 00H   PWDCON2 PDOST PDTRM1 PDTRM0 PDEXCL PDST1 PDST0   Initial value PWDCON2 is a special function register (SFR) to control PWMD.
Page 171: Pwmd Control Register 3 (Pwdcon3)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.15 PWMD Control Register 3 (PWDCON3) Address: 0F929H Access: R/W Access size: 8 bits Initial value: 00H   PWDCON3 PDSDE1 PDSDE0 PDSTSS PDSTS2 PDSTS1 PDSTS0   Initial value PWDCON3 is a special function register (SFR) to control PWMD.
Page 172: Pwme Period Registers (Pwepl, Pweph)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.16 PWME Period Registers (PWEPL, PWEPH) Address: 0F930H Access: R/W Access size: 8/16 bits Initial value: 0FFH PWEPL PEP7 PEP6 PEP5 PEP4 PEP3 PEP2 PEP1 PEP0 Initial value Address: 0F931H Access: R/W Access size: 8 bits...
Page 173: Pwme Duty Registers (Pwedl, Pwedh)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.17 PWME Duty Registers (PWEDL, PWEDH) Address: 0F932H Access: R/W Access size: 8/16 bits Initial value: 00H PWEDL PED7 PED6 PED5 PED4 PED3 PED2 PED1 PED0 Initial value Address: 0F933H Access: R/W Access size: 8 bits...
Page 174: Pwme Counter Registers (Pwech, Pwecl)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.18 PWME Counter Registers (PWECH, PWECL) Address: 0F934H Access: R/W Access size: 8/16 bits Initial value: 00H PWECL PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 Initial value Address: 0F935H Access: R/W Access size: 8 bits...
Page 175: Pwme Control Register 0 (Pwecon0)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.19 PWME Control Register 0 (PWECON0) Address: 0F936H Access: R/W Access size: 8/16 bits Initial value: 00H   PWECON0 PESDN PENEG PEIS1 PEIS0 PECS1 PECS0   Initial value PWECON0 is a special function register (SFR) to control PWME.
Page 176: Pwme Control Register 1 (Pwecon1)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.20 PWME Control Register 1 (PWECON1) Address: 0F937H Access: R/W Access size: 8 bits Initial value: 00H    PWECON1 PESTAT PEFLG PESDST PETGEN PERUN    Initial value PWECON1 is a special function register (SFR) to control PWME.
Page 177: Pwme Control Register 2 (Pwecon2)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.21 PWME Control Register 2 (PWECON2) Address: 0F938H Access: R/W Access size: 8/16 bits Initial value: 00H   PWECON2 PEOST PETRM1 PETRM0 PEEXCL PEST1 PEST0   Initial value PWECON2 is a special function register (SFR) to control PWME.
Page 178: Pwme Control Register 3 (Pwecon3)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.22 PWME Control Register 3 (PWECON3) Address: 0F939H Access: R/W Access size: 8 bits Initial value: 00H   PWECON3 PESDE1 PESDE0 PESTSS PESTS2 PESTS1 PESTS0   Initial value PWECON3 is a special function register (SFR) to control PWME.
Page 179: Pwmf Period Registers (Pwfpl, Pwfph)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.23 PWMF Period Registers (PWFPL, PWFPH) Address: 0F960H Access: R/W Access size: 8/16 bits Initial value: 0FFH PWFPL PFP7 PFP6 PFP5 PFP4 PFP3 PFP2 PFP1 PFP0 Initial value Address: 0F961H Access: R/W Access size: 8 bits...
Page 180: Pwmf0 Duty Registers (Pwf0Dl, Pwf0Dh)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.24 PWMF0 Duty Registers (PWF0DL, PWF0DH) Address: 0F962H Access: R/W Access size: 8/16 bits Initial value: 00H PWF0DL PF0D7 PF0D6 PF0D5 PF0D4 PF0D3 PF0D2 PF0D1 PF0D0 Initial value Address: 0F963H Access: R/W Access size: 8 bits...
Page 181: Pwmf1 Duty Registers (Pwf1Dl, Pwf1Dh)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.25 PWMF1 Duty Registers (PWF1DL, PWF1DH) Address: 0F964H Access: R/W Access size: 8/16 bits Initial value: 00H PWF1DL PF1D7 PF1D6 PF1D5 PF1D4 PF1D3 PF1D2 PF1D1 PF1D0 Initial value Address: 0F965H Access: R/W Access size: 8 bits...
Page 182: Pwmf2 Duty Registers (Pwf2Dl, Pwf2Dh)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.26 PWMF2 Duty Registers (PWF2DL, PWF2DH) Address: 0F966H Access: R/W Access size: 8/16 bits Initial value: 00H PWF2DL PF2D7 PF2D6 PF2D5 PF2D4 PF2D3 PF2D2 PF2D1 PF2D0 Initial value Address: 0F967H Access: R/W Access size: 8 bits...
Page 183: Pwmf Counter Registers (Pwfch, Pwfcl)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.27 PWMF Counter Registers (PWFCH, PWFCL) Address: 0F970H Access: R/W Access size: 8/16 bits Initial value: 00H PWFCL PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 Initial value Address: 0F971H Access: R/W Access size: 8 bits...
Page 184: Pwmf Control Register 0 (Pwfcon0)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.28 PWMF Control Register 0 (PWFCON0) Address: 0F972H Access: R/W Access size: 8/16 bits Initial value: 00H   PWFCON0 PFSDN PFNEG PFIS1 PFIS0 PFCS1 PFCS0   Initial value PWFCON0 is a special function register (SFR) to control PWMF.
Page 185: Pwmf Control Register 1 (Pwfcon1)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.29 PWMF Control Register 1 (PWFCON1) Address: 0F973H Access: R/W Access size: 8 bits Initial value: 00H    PWFCON1 PFSTAT PFFLG PFSDST PFTGEN PFRUN    Initial value PWFCON1 is a special function register (SFR) to control PWMF.
Page 186: Pwmf Control Register 2 (Pwfcon2)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.30 PWMF Control Register 2 (PWFCON2) Address: 0F974H Access: R/W Access size: 8/16 bits Initial value: 00H   PWFCON2 PFOST PFTRM1 PFTRM0 PFEXCL PFST1 PFST0   Initial value PWFCON2 is a special function register (SFR) to control PWMF0 to 2.
Page 187: Pwmf Control Register 3 (Pwfcon3)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.31 PWMF Control Register 3 (PWFCON3) Address: 0F975H Access: R/W Access size: 8 bits Initial value: 00H   PWFCON3 PFSDE1 PFSDE0 PFSTSS PFSTS2 PFSTS1 PFSTS0   Initial value PWFCON3 is a special function register (SFR) to control PWMF0 to 2.
Page 188: Pwmf Control Register 4 (Pwfcon4)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.32 PWMF Control Register 4 (PWFCON4) Address: 0F976H Access: R/W Access size: 8/16 bits Initial value: 10H   PWFCON4 PF2EN PF1EN PF0EN PF2POL PF1POL PF0POL   Initial value PWFCON4 is a special function register (SFR) to control PWMF0 to 2.
Page 189: Pwmf Control Register 5 (Pwfcon5)
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.2.33 PWMF Control Register 5 (PWFCON5) Address: 0F977H Access: R/W Access size: 8 bits Initial value: 00H   PWFCON5 PF2FLG PF1FLG PF0FLG PFDISL1 PFDISL0 PFUD   Initial value PWFCON5 is a special function register (SFR) to control PWMF0 to 2.
Page 190: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.3 Description of Operation When the PnRUN bit of the PWMn control register 1 (PWnCON1) is set to “1”, the PWMn counters (PWnCH, PWnCL) are set to an operating state (PnSTAT is set to “1”) on the first falling edge of the PWMn clock (PnCK) that is selected by the PWMn control register 0 (PWnCON0) and increment the count value on the 2nd falling edge.
Page 191 ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM After the PnRUN bit is set to “1”, counting starts in synchronization with the PWMn clock(PnCK). This causes an error of up to 1 clock pulse to the time the first PWMn interrupt is issued. The PWMn interrupt period from the second time is fixed.
Page 192: Start, Stop, And Clear Operations Of Pwm By External Input Control
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.3.1 Start, Stop, and Clear Operations of PWM by External Input Control Setting the PnTRM1, PnTRM0, PnST1, PnST0 bits of the PWMn Control Register 2 (PWnCON2) enables the start/stop/clear control of the PWM counters (PWnCH and PWnCL) using the external input that is selected by the PnSTSS, PnSTS2 to PnSTS0 bits of the PWMn Control Register 3 (PWnCON3).
Page 193: Pwmf Operation
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.3.3 PWMF Operation PWMF can output three types of wave form with the same period and different duties. Polarity of each wave form can be set individually by the combination of PFNEG and PFnPOL.
Page 194 ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM As PWMF has three duty registers, there is a setting update register to synchronize these changes. If you change the duty during PWMF operation, confirm that PFUD bit of PWFCON5 is “0” and then write “1” to it after setting as desired.
Page 195: Interrupt Of Pwm
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.3.4 Interrupt of PWM Interrupts of PWM contain the following four types: • Period match interrupt • Duty match interrupt • Count stop interrupt by external input • Emergency stop interrupt Figure 10-7 shows how to identify these interrupts when continuous mode and one-shot mode. For emergency stop interrupt, confirm that PnSDST bit of the PWnCON1 register is set to “1”...
Page 196: Specifying Port Registers
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.4 Specifying port registers To enable the PWM function, the applicable bit of each related port register needs to be set. See Chapter 15, “Port A”, Chapter 16, “Port B” and Chapter 17, “Port C” for detail about the port registers.
Page 197: Functioning Pb0 (Pwmc) As The Pwm Output
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.4.2 Functioning PB0 (PWMC) as the PWM output Set PB0MD1 bit (bit0 of PBMOD1 register) to “0”, and set PB0MD0 bit (bit0 of PBMOD0 register) to ”1” for specifying the PWM output as the secondary function of PB0 Reg.
Page 198: Functioning Pb7 (Pwmc) As The Pwm Output
ML610Q111/ML610Q112 User’s Manual Chapter 10 PWM 10.4.3 Functioning PB7 (PWMC) as the PWM output Set PB7MD1 bit (bit7 of PBMOD1 register) to “1”, and set PB7MD0 bit (bit7 of PBMOD0 register) to ”1” for specifying the PWM output as the fourthly function of PB7 Reg.
Page 199: Synchronous Serial Port
Chapter 11 Synchronous Serial Port...
Page 200: Overview
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11 Synchronous Serial Port 11.1 Overview This LSI includes one channel of the 8/16-bit synchronous serial port (SSIO) and can also be used to control the device incorporated with the SPI interface by using one GPIO as the chip enable pin.
Page 201: List Of Pins
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11.1.3 List of Pins Pin name Description PB3/SIN Receive data input. Used for the secondary function of the PB3 pin. PB5/SCK Synchronous clock input/output. Used for the secondary function of the PB5 pin.
Page 202: Description Of Registers
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11.2 Description of Registers 11.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Serial port 0 transmit/receive 0F280H SIO0BUFL 8/16 buffer L SIO0BUF Serial port 0 transmit/receive 0F281H...
Page 203: Serial Port Transmit/Receive Buffers (Sio0Bufl, Sio0Bufh)
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) Address: 0F280H Access: R/W Access size: 8 bits /16 bits Initial value: 00H SIO0BUFL S0B7 S0B6 S0B5 S0B4 S0B3 S0B2 S0B1 S0B0 Initial value Address: 0F281H...
Page 204: Serial Port Control Register (Sio0Con)
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11.2.3 Serial Port Control Register (SIO0CON) Address: 0F282H Access: R/W Access size: 8 bits Initial value: 00H        SIO0CON S0EN      ...
Page 205: Serial Port Mode Register 0 (Sio0Mod0)
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11.2.4 Serial Port Mode Register 0 (SIO0MOD0) Address: 0F284H Access: R/W Access size: 8 bits Initial value: 00H     SIO0MOD0 S0LG S0MD1 S0MD0 S0DIR     Initial value SIO0MOD0 is a special function register (SFR) to set mode of the synchronous serial port.
Page 206: Serial Port Mode Register 1 (Sio0Mod1)
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11.2.5 Serial Port Mode Register 1 (SIO0MOD1) Address: 0F285H Access: R/W Access size: 8 bits Initial value: 00H    SIO0MOD1 S0CKT S0CK3 S0CK2 S0CK1 S0CK0    Initial value SIO0MOD1 is a special function register (SFR) to set mode of the synchronous serial port.
Page 207: Description Of Operation
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11.3 Description of Operation 11.3.1 Transmit Operation When “1” is written to the S0MD1 bit and “0” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a transmit mode.
Page 208: Receive Operation
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11.3.2 Receive Operation When “0” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a receive mode.
Page 209: Transmit/Receive Operation
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11.3.3 Transmit/Receive Operation When “1” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a transmit/receive mode.
Page 210: Specifying Port Registers
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11.4 Specifying port registers For enable the SSIO function, each related port register needs to be set up. Refer to the Chapter 16, “Port B” for details of each register. 11.4.1 Functioning as the SSIO master mode SSIO is selected as the secondary function of PB5, PB4, and PB3 by setting PB5MD1-PB3MD1 bit (PBMOD1 register: bit5-3) to “0”...
Page 211: Functioning As The Ssio Slave Mode
User’s Manual ML610Q111/ML610Q112 Chapter 11 Synchronous Serial Port 11.4.2 Functioning as the SSIO slave mode SSIO is selected as the secondary function of PB5, PB4, and PB3 by setting PB5MD1-PB3MD1 bit (PBMOD1 register: bit5-3) to “0” and setting PB5MD0-PB3MD0 bit (PBMOD0 register: bit5-3) to “1”. It is the same setup as the case of master mode.
Page 212: Uart
Chapter 12 UART...
Page 213: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12 UART 12.1 Overview This LSI includes 2 channels of UART (Universal Asynchronous Receiver Transmitter) which is an asynchronous serial interface of a half-duplex. (A full-duplex is also possible by using 2 channels.) The use of UART requires setting of the tertiary/fourthly functions of Port B. For the tertiary/fourthly functions of Port B, see Chapter 16, “Port B”.
Page 214: List Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.1.3 List of Pins Pin name Function UART0 data input pin PB0/RXD0 Used for the primary function of the PB0 pin. UART0 data input pin PB5/RXD0 Used for the primary function of the PB5 pin.
Page 215 ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.2.2 UART0 Transmit/Receive Buffer (UA0BUF) Address: 0F290H Access: R/W Access size: 8 bits Initial value: 00H UA0BUF U0B7 U0B6 U0B5 U0B4 U0B3 U0B2 U0B1 U0B0 Initial value UA0BUF is a special function register (SFR) to store the transmitted/received data of the UART.
Page 216: Uart0 Control Register (Ua0Con)
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.2.4 UART0 Control Register (UA0CON) Address: 0F291H Access: R/W Access size: 8 bits Initial value: 00H        UA0CON U0EN        Initial value UA0CON is a special function register (SFR) to control start/stop communication of the UART.
Page 217: Uart0 Mode Register 0 (Ua0Mod0)
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.2.6 UART0 Mode Register 0 (UA0MOD0) Address: 0F292H Access: R/W Access size: 8/16 bits Initial value: 00H    UA0MOD0 U0RSS U0RSEL U0CK1 U0CK0 U0IO    Initial value UA0MOD0 is a special function register (SFR) to set the transfer mode of the UART.
Page 218: Uart1 Mode Register 0 (Ua1Mod0)
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.2.7 UART1 Mode Register 0 (UA1MOD0) Address: 0F29AH Access: R/W Access size: 8/16 bits Initial value: 00H    UA0MOD0 U1RSS U1RSEL U1CK1 U1CK0 U1IO    Initial value UA1MOD0 is a special function register (SFR) to set the transfer mode of the UART.
Page 219: Uart0 Mode Register 1 (Ua0Mod1)
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.2.8 UART0 Mode Register 1 (UA0MOD1) Address: 0F293H Access: R/W Access size: 8/16 bits Initial value: 00H  UA0MOD1 U0DIR U0NEG U0STP U0PT1 U0PT0 U0LG1 U0LG0  Initial value UA0MOD1 is a special function register (SFR) to set the transfer mode of the UART.
Page 220: Uart1 Mode Register 1 (Ua1Mod1)
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.2.9 UART1 Mode Register 1 (UA1MOD1) Address: 0F29BH Access: R/W Access size: 8/16 bits Initial value: 00H  UA1MOD1 U1DIR U1NEG U1STP U1PT1 U1PT0 U1LG1 U1LG0  Initial value UA1MOD1 is a special function register (SFR) to set the transfer mode of the UART.
Page 221: Uart0 Baud Rate Registers L, H (Ua0Brtl, Ua0Brth)
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.2.10 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) Address: 0F294H Access: R/W Access size: 8/16 bits Initial value: 0FFH UA0BRTL U0BR7 U0BR6 U0BR5 U0BR4 U0BR3 U0BR2 U0BR1 U0BR0 Initial value Address: 0F295H Access: R/W...
Page 222: Uart1 Baud Rate Registers L, H (Ua1Brtl, Ua1Brth)
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.2.11 UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH) Address: 0F29CH Access: R/W Access size: 8/16 bits Initial value: 0FFH UA1BRTL U1BR7 U1BR6 U1BR5 U1BR4 U1BR3 U1BR2 U1BR1 U1BR0 Initial value Address: 0F29DH Access: R/W...
Page 223: Uart0 Status Register (Ua0Stat)
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.2.12 UART0 Status Register (UA0STAT) Address: 0F296H Access: R/W Access size: 8 bits Initial value: 00H     UA0STAT U0FUL U0PER U0OER U0FER     Initial value UA0STAT is a special function register (SFR) to indicate the state of transmit or receive operation of the UART.
Page 224: Uart1 Status Register (Ua1Stat)
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.2.13 UART1 Status Register (UA1STAT) Address: 0F29EH Access: R/W Access size: 8 bits Initial value: 00H     UA1STAT U1FUL U1PER U1OER U1FER     Initial value UA1STAT is a special function register (SFR) to indicate the state of transmit or receive operation of the UART.
Page 225: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.3 Description of Operation 12.3.1 Transfer Data Format In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, 5 to 8 bits can be selected as data bit.
Page 226: Baud Rate
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.3.2 Baud rate Baud rates are generated by the baud generator. The baud rate generator generates a baud rate by counting the clock selected by the baud rate clock selection bits (UnCK1, UnCK0) of the UARTn mode register 0 (UAnMOD0). The count value of the baud rate generator can be set by writing it in the UARTn baud rate register H or L (UAnBRTH, UAnBRTL).
Page 227: Transmitted Data Direction
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.3.3 Transmitted Data Direction Figure 12-4 shows the relationship between the transmit/receive buffer and the transmitted/received data. Data length: 8 bits LSB transmission LSB reception U0B2 U0B0 U0B7 U0B6 U0B5 U0B4 U0B3 U0B1 MSB transmission...
Page 228: Transmit Operation
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.3.4 Transmit Operation Transmission is started by setting the UnIO bit of the UARTn mode register 0 (UA0MOD0) to “0” to select transmit mode and setting the UnEN bit of the UARTn control register (UAnCON) to “1”.
Page 229: Receive Operation
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.3.5 Receive Operation Select the received data pin using the UnRSEL bit of the UARTn mode register 0 (UAnMOD0). Select the receive mode by setting the UnIO bit of the UARTn mode register 0 (UAnMOD0) to "1". Then, set the UnEN bit of the UARTn control register (UAnCON) to "1"...
Page 230: Sampling Timing
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.3.5.1 Detection of Start Bit The Start bit is sampled using the baud rate generator clock (LSCLK, HSCLK) which selected by UnCK1, UnCK0 bits of UARTn mode register 0 (UAnMOD0). Therefore, the start bit detection may be delayed for one cycle of the baud rate generate clock at the maximum.
Page 231: Reception Margin
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.3.5.3 Reception Margin If there are any errors between the baud rate on the transmitter side and the baud rate to be generated by the baud rate generator of the LSI, those errors will be accumulated until the last stop bit in one frame is shifted in, causing the reception margin to be reduced.
Page 232: Specifying Port Registers
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.4 Specifying port registers To enable the UART function, the applicable bit of each related port register needs to be set. See Chapter 16, “Port B” for detail about the port registers. 12.4.1 Functioning PB1(TXD0) and PB0(RXD0) as the UART Set the PB1MD1 bit(bit1 of PBMOD1 register) to “1”...
Page 233: Functioning Pb4(Txd0) And Pb5(Rxd0) As The Uart
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.4.2 Functioning PB4(TXD0) and PB5(RXD0) as the UART Set the PB4MD1(bit4 of PBMOD1 register) to “1” and set the PB5MD1 bit (bit5 of PBMOD1 register) to “0”, and set the PB5MD0-PB4MD0 bits(bit5-4 of PBMOD0 register) to “0”, for specifying the UART as the primary function of PB5 and the tertiary function of PB4.
Page 234: Functioning Pb1(Txd1) And Pb2(Rxd1) As The Uart
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.4.3 Functioning PB1(TXD1) and PB2(RXD1) as the UART Set the PB1MD1 bit(bit1 of PBMOD1 register) to “1” and set the PB2MD1(bit2 of PBMOD1 register) to “0”, and set the PB1MD0 bit(bit1 of PBMOD0 register) to “1” and set the PB2MD0(bit2 of PBMOD0 register) to “0”, for specifying the UART as the fourthly function of PB1 and the primary function of PB2.
Page 235: Functioning Pb3(Txd1) And Pb2(Rxd1) As The Uart
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.4.4 Functioning PB3(TXD1) and PB2(RXD1) as the UART Set the PB3MD1 bit (bit3 of PBMOD1 register) to “1” and set the PB2MD1(bit2 of PBMOD1 register) to “0”, and set the PB3MD0-PB2MD0 bits(bit3-2 of PBMOD0 register) to “0”, for specifying the UART as the tertiary function of PB3 and the primary function of PB2.
Page 236: Functioning Pb4(Txd1) And Pb2(Rxd1) As The Uart
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.4.5 Functioning PB4(TXD1) and PB2(RXD1) as the UART Set the PB4MD1 bit(bit4 of PBMOD1 register) to “1” and set the PB2MD1(bit2 of PBMOD1 register) to “0”, and set the PB4MD0 bit(bit4 of PBMOD0 register) to “1” and set the PB2MD0(bit2 of PBMOD0 register) to “0”, for specifying the UART as the fourthly function of PB4 and the primary function of PB2.
Page 237: Functioning Pb1(Txd1) And Pb7(Rxd1) As The Uart
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.4.6 Functioning PB1(TXD1) and PB7(RXD1) as the UART Set the PB1MD1 bit (bit1 of PBMOD1 register) to “1” and set the PB7MD1(bit7 of PBMOD1 register) to “0”, and set the PB1MD0 bit(bit1 of PBMOD0 register) to “1” and set the PB7MD0(bit7 of PBMOD0 register) to “0”, for specifying the UART as the fourthly function of PB1 and the primary function of PB7.
Page 238: Functioning Pb3(Txd1) And Pb7(Rxd1) As The Uart
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.4.7 Functioning PB3(TXD1) and PB7(RXD1) as the UART Set the PB3MD1 bit(bit3 of PBMOD1 register) to “1” and set the PB7MD1(bit7 of PBMOD1 register) to “0”, and set the PB3MD0, PB7MD0 bits(bit3 and bit7 of PBMOD0 register) to “0”, for specifying the UART as the tertiary function of PB3 and the primary function of PB7.
Page 239: Functioning Pb4(Txd1) And Pb7(Rxd1) As The Uart
ML610Q111/ML610Q112 User’s Manual Chapter 12 UART 12.4.8 Functioning PB4(TXD1) and PB7(RXD1) as the UART Set the PB4MD1 bit (bit4 of PBMOD1 register) to “1” and set the PB7MD1(bit7 of PBMOD1 register) to “0”, and set the PB4MD0 bit(bit4 of PBMOD0 register) to “1” and set the PB7MD0(bit7 of PBMOD0 register) to “0”, for specifying the UART as the fourthly function of PB4 and the primary function of PB7.
Page 240: I2C Bus Interface Master
Chapter 13 C Bus Interface Master...
Page 241: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13 I C Bus Interface Master 13.1 Overview This LSI includes 1 channel of I C bus interface (master). The tertiary functions of Port B or the secondary functions of Port C are assigned to the I...
Page 242: Overviewdescription Of Registers
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13.2 OverviewDescription of Registers 13.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F2A0H C bus 0 receive register I2C0RD — 0F2A1H C bus 0 slave address register I2C0SA —...
Page 243: I2C Bus 0 Receive Register (I2C0Rd)
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13.2.2 C Bus 0 Receive Register (I2C0RD) Address: 0F2A0H Access: R Access size: 8 bits Initial value: 00H I2C0RD I20R7 I20R6 I20R5 I20R4 I20R3 I20R2 I20R1 I20R0 Initial value I2C0RD is a read-only special function register (SFR) to store receive data.
Page 244: I2C Bus 0 Slave Address Register (I2C0Sa)
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13.2.3 C Bus 0 Slave Address Register (I2C0SA) Address: 0F2A1H Access: R/W Access size: 8 bits Initial value: 00H I2C0SA I20A6 I20A5 I20A4 I20A3 I20A2 I20A1 I20A0 I20RW Initial value I2C0SA is a special function register (SFR) to set the address and the data direction bit of the slave device.
Page 245: I2C Bus 0 Transmit Data Register (I2C0Td)
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13.2.4 C Bus 0 Transmit Data Register (I2C0TD) Address: 0F2A2H Access: R/W Access size: 8 bits Initial value: 00H I2C0TD I20T7 I20T6 I20T5 I20T4 I20T3 I20T2 I20T1 I20T0 Initial value I2C0TD is a special function register (SFR) to set transmit data.
Page 246: I2C Bus 0 Control Register (I2C0Con)
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13.2.5 C Bus 0 Control Register (I2C0CON) Address: 0F2A3H Access: R/W Access size: 8 bits Initial value: 00H I2C0CON I20ACT — — — — I20RS I20SP I20ST — — —...
Page 247: I2C Bus 0 Mode Register (I2C0Mod)
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13.2.6 C Bus 0 Mode Register (I2C0MOD) Address: 0F2A4H Access: R/W Access size: 8 bits Initial value: 00H I2C0MOD — — — I20SYN I20DW1 I20DW0 I20MD I20EN — — —...
Page 248: I2C Bus 0 Status Register (I2C0Stat)
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13.2.7 C Bus 0 Status Register (I2C0STAT) Address: 0F2A5H Access: R Access size: 8 bits Initial value: 00H I2C0STAT — — — — — I20ER I20ACR I20BB — — —...
Page 249: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13.3 Description of Operation 13.3.1 Communication Operating Mode Communication is started when communication mode is selected by using the I C bus 0 mode register (I2C0MOD), the I function is enabled by using the I20EN bit, a slave address and a data direction bit are set in the I C bus 0 slave address register, and “1”...
Page 250: Communication Operation Timing
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13.3.2 Communication Operation Timing Figures 13-2 to 13-4 show the operation timing and control method for each communication mode. Reception Transmission Start Stop Repeated start Reception of Transmission of Transmission of...
Page 251 ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master Figure 13-5 shows the operation timing and control method when an acknowledgment error occurs. Acknowledgment error Register I2C0SA=”xxxxxxx0B” setting I2C0CON=”01H” I2C0CON=”02H” Value of I2C0SA I2CMINT I20ST I2C0RD Value of I2C0SA...
Page 252: Operation Waveforms
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13.3.3 Operation Waveforms Figure 13-7 shows the operation waveforms of the SDA and SCL signals and the I20BB flag. Table 13-1 shows the relationship between communication speeds and HSCLK clock counts.
Page 253: Specifying Port Registers
ML610Q111/ML610Q112 User’s Manual Chapter 13 I C bus Interface Master 13.4 Specifying port registers To enable the I C function, the applicable bit of each related port register needs to be set. See Chapter 16, “Port B” and Chapter 17, “Port C” for detail about the port registers.
Page 254: I2C Bus Interface Slave
Chapter 14 C Bus Interface Slave...
Page 255: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14 I C Bus Interface Slave 14.1 Overview This LSI includes 1 channel of I C bus interface (slave). The tertiary functions of Port B or the secondary functions of Port C are assigned to the I...
Page 256: List Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14.1.3 List of Pins Pin name Description C bus interface data input/output pin. PB6/SDA Used for the tertiary function of the PB6 pin. C bus interface clock input/output pin. PB5/SCL Used for the tertiary function of the PB5 pin.
Page 257 ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14.2 Description of Registers 14.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F2A8H C bus 1 receive register I2C1RD — 0F2A9H C bus 1 slave address register I2C1SA —...
Page 258: I2C Bus 1 Receive Register (I2C1Rd)
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14.2.2 C Bus 1 Receive Register (I2C1RD) Address: 0F2A8H Access: R Access size: 8 bits Initial value: 00H I2C1RD I21R7 I21R6 I21R5 I21R4 I21R3 I21R2 I21R1 I21R0 Initial value I2C1RD is a read-only special function register (SFR) to store receive data.
Page 259: I2C Bus 1 Slave Address Register (I2C1Sa)
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14.2.3 C Bus 1 Slave Address Register (I2C1SA) Address: 0F2A9H Access: R/W Access size: 8 bits Initial value: 00H I2C1SA I21A6 I21A5 I21A4 I21A3 I21A2 I21A1 I21A0 — — Initial value I2C1SA is a special function register (SFR) to set the slave address.
Page 260: I2C Bus 1 Transmit Data Register (I2C1Td)
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14.2.4 C Bus 1 Transmit Data Register (I2C1TD) Address: 0F2AAH Access: R/W Access size: 8 bits Initial value: 00H I2C1TD I21T7 I21T6 I21T5 I21T4 I21T3 I21T2 I21T1 I21T0 Initial value I2C1TD is a special function register (SFR) to set transmit data.
Page 261: I2C Bus 1 Control Register (I2C1Con)
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14.2.5 C Bus 1 Control Register (I2C1CON) Address: 0F2ABH Access: R/W Access size: 8 bits Initial value: 00H I2C1CON I21ACT — I21WT — — — — — — — —...
Page 262: I2C Bus 1 Mode Register (I2C1Mod)
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14.2.6 C Bus 1 Mode Register (I2C1MOD) Address: 0F2ACH Access: R/W Access size: 8 bits Initial value: 00H I2C1MOD — I21SIE I21PIE — — — — I21EN — — —...
Page 263: I2C Bus 1 Status Register (I2C1Stat)
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14.2.7 C Bus 1 Status Register (I2C1STAT) Address: 0F2ADH Access: R Access size: 8 bits Initial value: 00H I2C1STAT — — — I21TR I21SAA I21ER I21ACR I21BB — — —...
Page 264 ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave • I21TR (bit 4) The I21TR bit indicates status of transmission and receive. The I21TR bit is set to “1” when detecting data direction bit is “1”. The I21TR bit is reset to “0” when detecting stop condition, start condition, data direction bit is “0” and when I21EN bit of I2C1MOD0 is “0”.
Page 265: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14.3 Description of Operation 14.3.1 Communication Operating Mode The receive starts enabled after a slave address is specified to I2C1SA register, start and stop condition interrupts are set to enabled by using I2C1MOD register and set the I21EN bit to “1”.
Page 266: Communication Operation Timing
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14.3.2 Communication Operation Timing Figures 14-2 to 14-4 show the operation timing and control method for each communication mode. Transmission Reception Start Stop Repeated start Reception of Transmission of Transmission of...
Page 267: Operation Waveforms
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave When the values of the transmitted bit and the SDA pin do not coincide, the I21ER bit of the I2C bus 1 status register (I2C0STAT) is set to “1” and SDA pin remains the output until termination of the subsequent byte data communication.
Page 268: Specifying Port Registers
ML610Q111/ML610Q112 User’s Manual Chapter 14 I C bus Interface Slave 14.4 Specifying port registers To enable the I C function, the applicable bit of each related port register needs to be set. See Chapter 16, “Port B” and Chapter 17, “Port C” for detail about the port registers.
Page 269: Port A
Chapter 15 Port A...
Page 270: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 15 Port A 15 Port A 15.1 Overview This LSI includes Port A (PA0 to PA2) which is a 3-bit input/output port. Port A can have external interrupt, input of comparator and input of Successive Approximation Type A/D Converter. And, port A can have PWM, Timers, output of comparator, input of external clock, output of clock functions as secondary, tertiary and fourthly functions.
Page 271: Configuration
ML610Q111/ML610Q112 User’s Manual Chapter 15 Port A 15.1.2 Configuration Figure 15-1 shows the configuration of Port A. Pull-up Data bus Pull-down Controller PADIR PAMOD0,1 PACON0,1 PWMC,PWMD,PWME PortA CMP0OUT Output OUTCLK, LSCLK Controller TM9OUT, TMFOUT CLKIN, Trigger Inputs* EXI0-EXI2 CMP1P AIN0, AIN1...
Page 272: List Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 15 Port A 15.1.3 List of Pins Tertiary function Fourthly function Pin name Primary function Secondary function PA0/ Input/output port, EXI0/ External 0 interrupt, High-speed clock Timer 9 out AIN0/ SA-ADC 0 input, PWMC output output (OUTCLK)
Page 273 ML610Q111/ML610Q112 User’s Manual Chapter 15 Port A 15.2 Description of Registers 15.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F250H Port A data register  0F251H Port A direction register PADIR 0F252H Port A control register 0...
Page 274: Port A Data Register (Pad)
ML610Q111/ML610Q112 User’s Manual Chapter 15 Port A 15.2.2 Port A Data Register (PAD) Address: 0F250H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― ― ― PA2D PA1D PA0D ― ― ― ― ― Initial value PAD is a special function register (SFR) to set the value to be output to the Port A pin or to read the input level of the Port A.
Page 275: Port A Direction Register (Padir)
ML610Q111/ML610Q112 User’s Manual Chapter 15 Port A 15.2.3 Port A Direction Register (PADIR) Address: 0F251H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― ― ― PADIR PA2DIR PA1DIR PA0DIR ― ― ― ― ― Initial value PADIR is a special function register (SFR) to select the input/output mode of Port A.
Page 276: Port A Control Registers 0, 1 (Pacon0, Pacon1)
ML610Q111/ML610Q112 User’s Manual Chapter 15 Port A 15.2.4 Port A Control Registers 0, 1 (PACON0, PACON1) Address: 0F252H Access: R/W Access size: 8/16 bits Initial value: 00H ― ― ― ― ― PACON0 PA2C0 PA1C0 PA0C0 ― ― ― ―...
Page 277: Port A Mode Registers 0 (Pamod0, Pamod1))
ML610Q111/ML610Q112 User’s Manual Chapter 15 Port A 15.2.5 Port A Mode Registers 0 (PAMOD0, PAMOD1)) Address: 0F254H Access: R/W Access size: 8/16 bits Initial value: 00H ― ― ― ― ― PAMOD0 PA2MD0 PA1MD0 PA0MD0 ― ― ― ― ―...
Page 278: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 15 Port A 15.3 Description of Operation 15.3.1 Input/Output Port Functions For each pin of Port A, either output or input is selected by setting the Port A direction register (PADIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port A control registers 0 and 1 (PACON0 and PACON1).
Page 279: Port B
Chapter 16 Port B...
Page 280: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 16 Port B 16 Port B 16.1 Overview This LSI includes Port B (PB0 to PB7) which is an 8-bit input/output port. Port B can have external interrupt, input of comparator and input of Successive Approximation Type A/D Converter.
Page 281: Configuration
ML610Q111/ML610Q112 User’s Manual Chapter 16 Port B 16.1.2 Configuration Figure 16-1 shows the configuration of Port B. Pull-up Data bus Pull-down Controller PWMC, PWMD, PWME, PBDIR PWMF0, PWMF1, PWMF2 PBMOD0,1 PBCON0,1 TXD0 , TXD1 SCL, SDA, SOUT, SCK PortB CMP1OUT,...
Page 282: List Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 16 Port B 16.1.3 List of Pins Tertiary function Fourthly function Pin name Primary function Secondary function PB0/ Input/output port, EXI4/ External 4 interrupt, AIN2/ SA-ADC 2 input, High-speed clock Comparator 1 output PWMC output RXD0/...
Page 283: Description Of Registers
ML610Q111/ML610Q112 User’s Manual Chapter 16 Port B 16.2 Description of Registers 16.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F258H Port B data register  0F259H Port B direction register PBDIR 0F25AH Port B control register 0...
Page 284: Port B Data Register (Pbd)
ML610Q111/ML610Q112 User’s Manual Chapter 16 Port B 16.2.2 Port B Data Register (PBD) Address: 0F258H Access: R/W Access size: 8 bits Initial value: 00H PB7D PB6D PB5D PB4D PB3D PB2D PB1D PB0D Initial value PBD is a special function register (SFR) to set the value to be output to the Port B pin or to read the input level of the Port B.
Page 285: Port B Direction Register (Pbdir)
ML610Q111/ML610Q112 User’s Manual Chapter 16 Port B 16.2.3 Port B Direction Register (PBDIR) Address: 0F259H Access: R/W Access size: 8 bits Initial value: 00H PBDIR PB7DIR PB6DIR PB5DIR PB4DIR PB3DIR PB2DIR PB1DIR PB0DIR Initial value PBDIR is a special function register (SFR) to select the input/output mode of Port B.
Page 286: Port B Control Registers 0, 1 (Pbcon0, Pbcon1)
ML610Q111/ML610Q112 User’s Manual Chapter 16 Port B 16.2.4 Port B Control Registers 0, 1 (PBCON0, PBCON1) Address: 0F25AH Access: R/W Access size: 8/16 bits Initial value: 00H PBCON0 PB7C0 PB6C0 PB5C0 PB4C0 PB3C0 PB2C0 PB1C0 PB0C0 Initial value Address: 0F25BH...
Page 287 ML610Q111/ML610Q112 User’s Manual Chapter 16 Port B When output mode is selected When input mode is selected Setting of PB3 pin (PB3DIR bit = “0”) (PB3DIR bit = “1”) PB3C1 PB3C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output...
Page 288: Port B Mode Registers 0 (Pbmod0, Pbmod1)
ML610Q111/ML610Q112 User’s Manual Chapter 16 Port B 16.2.5 Port B Mode Registers 0 (PBMOD0, PBMOD1) Address: 0F25CH Access: R/W Access size: 8/16 bits Initial value: 00H PBMOD0 PB7MD0 PB6MD0 PB5MD0 PB4MD0 PB3MD0 PB2MD0 PB1MD0 PB0MD0 Initial value Address: 0F25DH Access: R/W...
Page 289 ML610Q111/ML610Q112 User’s Manual Chapter 16 Port B • PB3MD1, PB3MD0 (bit 3) The PB3MD1 and PB3MD0 bits are used to select the primary, secondary, tertiary and fourthly functions of the PB3 pin. PB3MD1 PB3MD0 Description General-purpose input/output mode (initial value)
Page 290: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 16 Port B 16.3 Description of Operation 16.3.1 Input/Output Port Functions For each pin of Port B, either output or input is selected by setting the Port B direction register (PBDIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port B control registers 0 and 1 (PBCON0 and PBCON1).
Page 291: Port C
Chapter 17 Port C...
Page 292: Overview
C pins (SCL, SDA), Timers output pins (TM9OUT, TMFOUT) can be used as the secondary, tertiary and fourthly functions. Note: When used as ML610Q111, the PC4 to PC7 ports do not exist, and the PC4 to PC7 special function registers (SFRs) do not perform. FEUL610Q111...
Page 293: Configuration
ML610Q111/ML610Q112 User’s Manual Chapter 17 Port C 17.1.2 Configuration Figure 17-1 shows the configuration of Port C. Pull-up Data bus Pull-down Controller PCDIR PCMOD0,1 PCCON0,1 PWMF0, PWMF1, PWMF2 Port C SCL, SDA Output PC0 to PC7 TM9OUT, TMFOUT Controller SCL, SDA...
Page 294: List Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 17 Port C 17.1.3 List of Pins Tertiary function Fourthly function Pin name Primary function Secondary function  PC0/ Input/output port PWMF0 output Timer 9 output   PC1/ Input/output port PWMF1 output   PC2/...
Page 295 ML610Q111/ML610Q112 User’s Manual Chapter 17 Port C 17.2 Description of Registers 17.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F260H Port C data register  0F261H Port C direction register PCDIR 0F262H Port C control register 0...
Page 296: Port C Data Register (Pcd)
The PC7D to PC0D bits are used to set the output value of the Port C pin in output mode and to read the pin level of the Port C pin in input mode. When used as ML610Q111, setting the value of PC7D to PC4D do not affect an applicable ports. PC0D Description Output or input level of the PC0 pin: ”L”...
Page 297: Port C Direction Register (Pcdir)
• PC7DIR-PC0DIR (bits 7 to 0) The PC7DIR to PC0DIR pins are used to set the input/output direction of the Port C pin. When used as ML610Q111, setting the value of PC7DIR to PC4DIR do not affect an applicable ports. PC0DIR...
Page 298: Port C Control Registers 0, 1 (Pccon0, Pccon1)
When used as ML610Q111, setting the value of PC7C1 to PC4C1, PC7C0 to PC4C0 do not affect an applicable ports. * High-impedance output means the status that both of H level output and L level output turn off.
Page 299 ML610Q111/ML610Q112 User’s Manual Chapter 17 Port C When output mode is selected When input mode is selected Setting of PC3 pin (PC3DIR bit = “0”) (PC3DIR bit = “1”) PC3C1 PC3C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output...
Page 300: Port C Mode Registers 0 (Pcmod0, Pcmod1)
PCMOD0 and PCMOD1 are special function register (SFR) to select the primary, secondary, tertiary and fourthly function of Port C. When used as ML610Q111, setting the value of PC7MD1 to PC4MD1, PC7MD0 to PC4MD0 do not affect an applicable ports.
Page 301 ML610Q111/ML610Q112 User’s Manual Chapter 17 Port C • PC3MD1, PC3MD0 (bit 3) The PC3MD1 and PC3MD0 bits are used to select the primary, secondary, tertiary and fourthly functions of the PC3 pin. PC3MD1 PC3MD0 Description General-purpose input/output mode (initial value)
Page 302: Description Of Operation
In input mode, the input level of each pin of Port C can be read from the Port C data register (PCD). Note: When used as ML610Q111, the PC4 to PC7 ports do not exist, and the PC4 to PC7 special function registers (SFRs) do not perform.
Page 303: Port D
Chapter 18 Port D...
Page 304: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 18 Port D 18 Port D 18.1 Overview This LSI includes Port D (PD0 to PD5) which is a 6-bit input/output port.(only for ML610Q112) 18.1.1 Features • Allows selection of high-impedance output, P-channel open drain output, N-channel open drain output, or CMOS output for each bit in output mode.
Page 305: List Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 18 Port D 18.1.3 List of Pins Pin name Primary function Input/output port Input/output port Input/output port Input/output port Input/output port Input/output port FEUL610Q111 18-2...
Page 306 ML610Q111/ML610Q112 User’s Manual Chapter 18 Port D 18.2 Description of Registers 18.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F268H Port D data register  0F269H Port D direction register PDDIR 0F26AH Port D control register 0...
Page 307: Port D Data Register (Pdd)
ML610Q111/ML610Q112 User’s Manual Chapter 18 Port D 18.2.2 Port D Data Register (PDD) Address: 0F268H Access: R/W Access size: 8 bits Initial value: 00H ― ― PD5D PD4D PD3D PD2D PD1D PD0D ― ― Initial value PDD is a special function register (SFR) to set the value to be output to the Port D pin or to read the input level of the Port D.
Page 308: Port D Direction Register (Pddir)
ML610Q111/ML610Q112 User’s Manual Chapter 18 Port D 18.2.3 Port D Direction Register (PDDIR) Address: 0F269H Access: R/W Access size: 8 bits Initial value: 00H ― ― PDDIR PD5DIR PD4DIR PD3DIR PD2DIR PD1DIR PD0DIR ― ― Initial value PDDIR is a special function register (SFR) to select the input/output mode of Port D.
Page 309: Port D Control Registers 0, 1 (Pdcon0, Pdcon1)
ML610Q111/ML610Q112 User’s Manual Chapter 18 Port D 18.2.4 Port D Control Registers 0, 1 (PDCON0, PDCON1) Address: 0F26AH Access: R/W Access size: 8/16 bits Initial value: 00H ― ― PDCON0 PD5C0 PD4C0 PD3C0 PD2C0 PD1C0 PD0C0 ― ― Initial value...
Page 310 ML610Q111/ML610Q112 User’s Manual Chapter 18 Port D When output mode is selected When input mode is selected Setting of PD3 pin (PD3DIR bit = “0”) (PD3DIR bit = “1”) PD3C1 PD3C0 Description High-impedance output (initial value) High-impedance input P-channel open drain output...
Page 311: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 18 Port D 18.3 Description of Operation 18.3.1 /Output Port Functions Input For each pin of Port D, either output or input is selected by setting the Port D direction register (PDDIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port D control registers 0 and 1 (PDCON0 and PDCON1).
Page 312: Port Ab Interrupts
Chapter 19 Port AB Interrupts...
Page 313: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 19 Port AB Interrupts 19 Port AB Interrupts 19.1 Overview This LSI can have the external interrupts corresponding to seven ports. 19.1.1 Features • All bits support a maskable interrupt function. • Allows selection of interrupt disabled mode, falling-edge interrupt mode, rising-edge interrupt mode, or both-edge interrupt mode for each bit.
Page 314: Port Ab Interrupt Control Registers 0, 1 (Pabicon0, Pabicon1)
ML610Q111/ML610Q112 User’s Manual Chapter 19 Port AB Interrupts 19.2.2 Port AB Interrupt Control Registers 0, 1 (PABICON0, PABICON1) Address: 0F024H Access: R/W Access size: 8 bits Initial value: 00H  PABICON0 PB3E0 PB2E0 PB1E0 PB0E0 PA2E0 PA1E0 PA0E0  Initial value...
Page 315: Port Ab Interrupt Control Register 2 (Pabicon2)
ML610Q111/ML610Q112 User’s Manual Chapter 19 Port AB Interrupts 19.2.3 Port AB Interrupt Control Register 2 (PABICON2) Address: 0F026H Access: R/W Access size: 8 bits Initial value: 00H  PABICON2 PB3SM PB2SM PB1SM PB0SM PA2SM PA1SM PA0SM  Initial value PABICON2 is a special function register (SFR) to select detection of signal edge for interrupts with or without sampling.
Page 316: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 19 Port AB Interrupts 19.3 Description of Operation 19.3.1 Interrupt Request When an interrupt edge selected by the port AB interrupt control registers 0, 1, 2 (PABICON0, PABICON1, PABICON2) occurs at the external interrupt pins EXI0-2, EXI4-7 (PA0-2, PB0-3), the corresponding maskable Pxx interrupt (PA0INT–PA2INT, PB0INT-PB3INT) occurs.
Page 317: Successive Approximation Type A/D Converter
Chapter 20 Successive Approximation Type A/D Converter...
Page 318: Overview
This LSI has a built-in 6-channel or 8-channel successive approximation type A/D converter (SA-ADC). 20.1.1 Features • Built-in sample/hold 10-bit successive approximation type A-D converter, which enables channel selection from 6 channels or 8 channels (ML610Q111: 6-channel, ML610Q112: 8-channel) 20.1.2 Configuration Figure 20-1 shows the configuration of SA-ADC. 10-bit...
Page 319 ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.1.3 List of Pins Pin name Description Successive approximation type A/D converter input pin 0 PA0/AIN0 Used for the primary function of the PA0 pin Successive approximation type A/D converter input pin 1...
Page 320: Description Of Registers
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2 Description of Registers 20.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F2D0H SA-ADC result register 0L SADR0L 8/16 SADR0 0F2D1H SA-ADC result register 0H...
Page 321: Sa-Adc Result Register 0L (Sadr0L)
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2.2 SA-ADC Result Register 0L (SADR0L) Address: 0F2D0H Access: R Access size: 8/16 bits Initial value: 00H       SADR0L SAR03 SAR02    ...
Page 322: Sa-Adc Result Register 1L (Sadr1L)
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2.4 SA-ADC Result Register 1L (SADR1L) Address: 0F2D2H Access: R Access size: 8/16 bits Initial value: 00H       SADR1L SAR13 SAR12    ...
Page 323: Sa-Adc Result Register 2L (Sadr2L)
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2.6 SA-ADC Result Register 2L (SADR2L) Address: 0F2D4H Access: R Access size: 8/16 bits Initial value: 00H       SADR2L SAR23 SAR22    ...
Page 324: Sa-Adc Result Register 3L (Sadr3L)
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2.8 SA-ADC Result Register 3L (SADR3L) Address: 0F2D6H Access: R Access size: 8/16 bits Initial value: 00H       SADR3L SAR33 SAR32    ...
Page 325: Sa-Adc Result Register 4L (Sadr4L)
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2.10 SA-ADC Result Register 4L (SADR4L) Address: 0F2D8H Access: R Access size: 8/16 bits Initial value: 00H       SADR4L SAR43 SAR42    ...
Page 326: Sa-Adc Result Register 5L (Sadr5L)
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2.12 SA-ADC Result Register 5L (SADR5L) Address: 0F2DAH Access: R Access size: 8/16 bits Initial value: 00H       SADR5L SAR53 SAR52    ...
Page 327: Sa-Adc Result Register 6L (Sadr6L)
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2.14 SA-ADC Result Register 6L (SADR6L) Address: 0F2DCH Access: R Access size: 8/16 bits Initial value: 00H       SADR6L SAR63 SAR62    ...
Page 328: Sa-Adc Result Register 7L (Sadr7L)
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2.16 SA-ADC Result Register 7L (SADR7L) Address: 0F2DEH Access: R Access size: 8/16 bits Initial value: 00H       SADR7L SAR73 SAR72    ...
Page 329: Sa-Adc Control Register 0 (Sadcon0)
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2.18 SA-ADC Control Register 0 (SADCON0) Address: 0F2F0H Access: R/W Access size: 8/16 bits Initial value: 00H        SADCON0 SALP    ...
Page 330: Sa-Adc Control Register 1 (Sadcon1)
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2.19 SA-ADC Control Register 1 (SADCON1) Address: 0F2F1H Access: R/W Access size: 8 bits Initial value: 00H        SADCON1 SARUN    ...
Page 331: Sa-Adc Mode Register 0 (Sadmod0)
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.2.20 SA-ADC Mode Register 0 (SADMOD0) Address: 0F2F2H Access: R/W Access size: 8 bits Initial value: 00H SADMOD0 SACH7 SACH6 SACH5 SACH4 SACH3 SACH2 SACH1 SACH0 Initial value SADMOD0 is a special function register (SFR) used to select A/D conversion channel(s).
Page 332 • SACH6 (bit 6) SACH6 Description Stops conversion on channel 6. (Initial value) Performs conversion on channel 6. Don't set it for ML610Q111. • SACH7 (bit 7) SACH7 Description Stops conversion on channel 7. (Initial value) Performs conversion on channel 7.
Page 333: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.3 Description of Operation 20.3.1 Settings of A/D Conversion Channels According to the setting of SA-ADC mode register 0 (SADMOD0), A/D conversion is performed as shown below and A/D conversion results are stored in the SA-ADC result register.
Page 334: Operation Of The Successive Approximation A/D Converter
ML610Q111/ML610Q112 User’s Manual Chapter 20 Successive Approximation Type A/D Converter 20.3.2 Operation of the Successive Approximation A/D Converter Use the following procedure to operate the SA-ADC: 1. Before starting the SA-ADC, start oscillation of the high-speed clock (HSCLK) and wait until the oscillation stabilizes.
Page 335: Voltage Level Supervisor
Chapter 21 Voltage Level Supervisor...
Page 336: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 21 Voltage Level Supervisor 21 Voltage Level Supervisor 21.1 Overview This LSI includes two channels of the voltage level supervisor (VLS). 21.1.1 Features • Accuracy: ±3% (Typ. ) • The threshold voltages of VLS0 (V fall) : 2.85V (Typ. ) rise) : 2.92V (Typ.
Page 337: Description Of Registers
ML610Q111/ML610Q112 User’s Manual Chapter 21 Voltage Level Supervisor 21.2 Description of Registers 21.2.1 List of Registers Symbol Address Name Symbol (Word) Size Initial value (Byte) 0F0D8H Voltage level supervisor control register 0 VLSCON0 8/16 VLSCON 0F0D9H Voltage level supervisor control register 1...
Page 338 ML610Q111/ML610Q112 User’s Manual Chapter 21 Voltage Level Supervisor 21.2.2 Voltage Level Supervisor Control Register 0 (VLSCON0) Address: 0F0D8H Access: R/W Access size: 8 bits Initial value: 00H      VLSCON0 DVLSSP VLS1LV1 VLS1LV0    ...
Page 339 ML610Q111/ML610Q112 User’s Manual Chapter 21 Voltage Level Supervisor 21.2.3 Voltage Level Supervisor Control Register 1 (VLSCON1) Address: 0F0D9H Access: R/W Access size: 8 bits Initial value: 11H     VLSCON1 VLS1ST ENVLS1 VLS0ST ENVLS0    ...
Page 340 ML610Q111/ML610Q112 User’s Manual Chapter 21 Voltage Level Supervisor 21.2.4 Voltage Level Supervisor Mode Register (VLSMOD) Address: 0F0DAH Access: R/W Access size: 8 bits Initial value: 00H VLS1SEL VLS0SEL       VLSMOD     ...
Page 341: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 21 Voltage Level Supervisor 21.3 Description of Operation 21.3.1 Operation of Voltage Level Supervisor For the VLS, the ENVLSn bit of the VLS control register 1 (VLSCON1) controls ON/OFF, the VLP0SEL0 bit of VLSMOD controls enable/disable of the low level detector reset function of VLS0, and VLP1SEL1 bit of VLSMOD controls enable/disable of the interrupt request function of VLS1..
Page 342: Analog Comparator
Chapter 22 Analog Comparator...
Page 343: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 22 Analog Comparator 22 Analog Comparator 22.1 Overview This LSI includes 2 channels of analogue comparator. Voltage comparison (differential input) between two pins (CMP0P, CMP0M) that are input to the comparator is available. 22.1.1 Features • The comparator output can generate an interrupt.
Page 344: List Of Pins
ML610Q111/ML610Q112 User’s Manual Chapter 22 Analog Comparator 22.1.3 List of Pins Pin name Description PB4/CMP0P Analog comparator 0 non-inverted input pin PB5/CMP0M Analog comparator 0 inverted input pin PA2/CMP0OUT Analog comparator 0 output pin PA1/CMP1P Analog comparator 1 non-inverted input pin...
Page 345: Comparator 0 Control Register 0 (Cmp0Con0)
ML610Q111/ML610Q112 User’s Manual Chapter 22 Analog Comparator 22.2.2 Comparator 0 control register 0 (CMP0CON0) Address: 0F950H Access: R/W Access size: 8 bits Initial value: 00H — — — — — — CMP0D CMP0EN CMP0CON0 — — — — — —...
Page 346: Comparator 0 Control Register 1 (Cmp0Con1)
ML610Q111/ML610Q112 User’s Manual Chapter 22 Analog Comparator 22.2.3 Comparator 0 control register 1 (CMP0CON1) Address: 0F951H Access: R/W Access size: 8 bits Initial value: 00H CMP0 CMP0 CMP0 CMP0CON1 CMP0E1 CMP0E0 — — — — — — Initial value CMP0CON1 is a special function register (SFR) to control the comparator 0 interrupt.
Page 347: Comparator 0 Control Register 2 (Cmp0Con2)
ML610Q111/ML610Q112 User’s Manual Chapter 22 Analog Comparator 22.2.4 Comparator 0 control register 2 (CMP0CON2) Address: 0F952H Access: R/W Access size: 8 bits Initial value: 08H CMP0RF CMP0RF CMP0RF CMP0RF CMP0CON2 — — — — — — — — Initial value CMP0CON2 is a special function register (SFR) to select the reference voltage of the comparator 0.
Page 348: Comparator 1 Control Register 0 (Cmp1Con0)
ML610Q111/ML610Q112 User’s Manual Chapter 22 Analog Comparator 22.2.5 Comparator 1 control register 0 (CMP1CON0) Address: 0F954H Access: R/W Access size: 8 bits Initial value: 00H CMP1CON0 — — — — — — CMP1D CMP1EN — — — — — —...
Page 349: Comparator 1 Control Register 1 (Cmp1Con1)
ML610Q111/ML610Q112 User’s Manual Chapter 22 Analog Comparator 22.2.6 Comparator 1 control register 1 (CMP1CON1) Address: 0F955H Access: R/W Access size: 8 bits Initial value: 00H CMP1 CMP1 CMP1CON1 CMP1E1 CMP1E0 — — — — — — — — Initial value CMP1CON1 is a special function register (SFR) to control the Comparator 1 interrupt.
Page 350: Comparator 1 Control Register 2 (Cmp1Con2)
ML610Q111/ML610Q112 User’s Manual Chapter 22 Analog Comparator 22.2.7 Comparator 1 control register 2 (CMP1CON2) Address: 0F956H Access: R/W Access size: 8 bits Initial value: 08H CMP1RF CMP1RF CMP1RF CMP1RF CMP1CON2 — — — — — — — — Initial value CMP1CON2 is a special function register (SFR) to select the reference voltage of the Comparator 1.
Page 351: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 22 Analog Comparator 22.3 Description of Operation 22.3.1 Comparator Functions The comparator compares the input voltages of the CMPnP and CMPnM pins to output the result to the CMPnD bit of the comparator control register 0 (CMPnCON0).
Page 352: Interrupt Request
ML610Q111/ML610Q112 User’s Manual Chapter 22 Analog Comparator 22.3.2 Interrupt Request When an interrupt edge selected by the comparator control register 1 (CMPnCON1) occurs on the comparison result of the comparator, a comparator interrupt (CMPnINT) is generated. For the comparator interrupt, the edge can be selected.
Page 353: Data Flash Memory
Chapter 23 Data Flash Memory...
Page 354: Overview
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23 Data Flash Memory 23.1 Overview This LSI includes the data flash memory (data memory space (4 Kbytes: 1 Kbytes x 4 sectors)) that is rewritable by using a special function register (SFR) programmatically.
Page 355 ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.2 Description of Registers 23.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F0E0H Flash address register L FLASHAL 8/16 FLASHA 0F0E1H Flash address register H FLASHAH 0F0E2H...
Page 356: Flash Address Register (Flashal,H)
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.2.2 Flash Address Register (FLASHAL,H) Address: 0F0E0H Access: R/W Access size: 8/16 bits Initial value: 00H FLASHAL Initial value Address: 0F0E1H Access: R/W Access size: 8 bits Initial value: 00H FLASHAH FA15...
Page 357: Flash Data Register (Flashdl,H)
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.2.3 Flash Data Register (FLASHDL,H) Address: 0F0E2H Access: R/W Access size: 8/16 bits Initial value: 00H FLASHDL Initial value Address: 0F0E3H Access: R/W Access size: 8 bits Initial value: 00H FLASHDH FD15...
Page 358: Flash Control Register (Flashcon)
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.2.4 Flash Control Register (FLASHCON) Address: 0F0E4H Access: W Access size: 8 bits Initial value: 00H — — — — — — FSERS FERS FLASHCON — — — — — — Initial value FLASHCON is a write-only special function register (SFR) to control the block erase or the sector erase for the flash memory rewrite.
Page 359: Flash Accepter (Flashacp)
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.2.5 Flash Accepter (FLASHACP) Address: 0F0E5H Access: W Access size: 8 bits Initial value: 00H fac7 fac6 fac5 fac4 fac3 fac2 fac1 fac0 FLASHACP Initial value FLASHACP is a write-only special function register (SFR) to control the sector erase, the block erase for the flash memory rewrite or enable/disable the 1-word write operation.
Page 360: Flash Segment Register (Flashseg)
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.2.6 Flash Segment Register (FLASHSEG) Address: 0F0E6H Access: R/W Access size: 8 bits Initial value: 00H FLASHSEG — — — — — — FSEG1 FSEG0 — — — — — — Initial value FLASHSEG is a special function register (SFR) that sets the flash memory rewrite segment address.
Page 361: Flash Protection Register (Flashprt)
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.2.8 Flash Protection Register (FLASHPRT) Address: 0F0E8H Access: R/W Access size: 8 bits Initial value: 00H FLASHPRT — — — — FPRT3 FPRT2 FPRT1 FPRT0 — — — — Initial value FLASHPRT is a special function register (SFR) to control the sector erase, block erase, and 1-word write in the segment 2 0000H to 03FFH, 0400H to 07FFH, 0800H to 0BFFH, or 0C00H to 0FFFH.
Page 362 ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory • FPRT3 (bit 3) The FPRT3 is a bit to control the sector erase, block erase, and 1-word write in the segment 2 0C00H to 0FFFH. Writing “1” to FPRT3 sets FPRT3 to “1”, and disables the subsequent sector erases, block erases, and 1-word writes in the segment 2 0C00H to 0FFFH.
Page 363: Flash Erase Abort Source Select Register (Flasheas)
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.2.9 Flash Erase Abort Source Select Register (FLASHEAS) Address: 0F0EEH Access: R/W Access size: 8 bits Initial value: 00H FLASHEAS FEPB3S FEPB2S FEPB1S FEPB0S — FEPA2S FEPA1S FEPA0S — Initial value FLASHEAS is a special function register (SFR) to select the external interrupt to abort the flash erase operation.
Page 364: Flash Erase Status Register (Flashest)
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.2.10 Flash Erase Status Register (FLASHEST) Address: 0F0EFH Access: R/W Access size: 8 bits Initial value: 00H FLASHEST ESTAT — — — — — — — — — — — — —...
Page 365: Description Of Operation
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.3 Description of Operation The rewrite function includes the sector erase function that erases by 1K bytes, the block erase function that erases by 4K bytes, and the 1-word write function that writes by 1 word (2 bytes).
Page 366: Sector Erase Function
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.3.1 Sector Erase Function This function erases the flash memory data by sector (1K bytes). When writing “01H” to the flash self register (FLASHSLF), writing “0FAH” and “0F5H” to the flash acceptor (FLASHACP), setting block addresses for the flash segment register (FLASHSEG) and the flash address register H (FLASHAH), and then writing “1”...
Page 367 ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory Figure 23-2 shows a sample program of sector erase. offset FLASHAH ; EA <- FLASHAH address #0FAH ; Flash acceptor enable data #0F5H ; Flash acceptor enable data #(offset FLASHACP)&0FFH #(offset FLASHACP)>>8 ;...
Page 368: Block Erase Function
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.3.2 Block Erase Function This function erases the flash memory data by block (4K bytes). When writing “01H” to the flash self register (FLASHSLF), writing “0FAH” and “0F5H” to the flash acceptor (FLASHACP), setting block addresses for the flash segment register (FLASHSEG) and the flash address register H (FLASHAH), and then writing “1”...
Page 369 ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory Figure 23-4 shows a sample program of erase. block offset FLASHAH ; EA <- FLASHAH address #0FAH ; Flash acceptor enable data #0F5H ; Flash acceptor enable data #(offset FLASHACP)&0FFH #(offset FLASHACP)>>8 ;...
Page 370: 1-Word Write Function
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.3.3 1-Word Write Function This function writes data to the flash memory by 1 word (2 bytes). Write “01H” to the flash self register (FLASHSLF) and write “0FAH” and “0F5H” to the flash acceptor (FLASHACP) and set the address in the flash segment register (FLASHSEG) and the flash address register L, H (FLASHAL,H).
Page 371 ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory offset FLASHAL ; EA <- FLASHAL address #0FAH ; Flash acceptor enable data #0F5H ; Flash acceptor enable data #02H ; Address increment data #00H #(offset FLASHACP)&0FFH #(offset FLASHACP)>>8 ; ER4 <- FLASHACP address...
Page 372: Notes In Use
ML610Q111/ML610Q112 User’s Manual Chapter 23 Data Flash Memory 23.3.4 Notes in Use When the power is down or the operation is terminated forcibly during sector erase, block erase, or 1-word write, retry the sector erase or block erase and rewrite the sector block area.
Page 373 Chapter 24 On-chip Debug...
Page 374: On-Chip Debug Function
ML610Q111/ML610Q112 User's Manual Chapter 24 On-chip Debug 24 On-Chip Debug Function 24.1 Overview This LSI has an on-chip debug function allowing Flash memory rewriting. The on-chip debug emulator (uEASE) is connected to this LSI to perform the on-chip debug function.
Page 375 Appendixes...
Page 376: Appendix
ML610Q111/ML610Q112 User’s Manual Appendix A Registers Appendix A Registers Contents of Registers Symbol Symbol Initial Address Name Size (Byte) (Word) value  0F000H Data segment register  0F001H Reset status register RSTAT Undefined 0F002H Frequency control register 0 FCON0 8/16...
Page 377 ML610Q111/ML610Q112 User’s Manual Appendix A Registers Symbol Symbol Initial Address Name Size (Byte) (Word) value 0F252H Port A control register 0 PACON0 8/16 PACON 0F253H Port A control register 1 PACON1 0F254H Port A mode register 0 PAMOD0 8/16 PAMOD...
Page 378: Appendix A Registers
ML610Q111/ML610Q112 User’s Manual Appendix A Registers Symbol Symbol Initial Address Name Size (Byte) (Word) value 0F2D2H SA-ADC result register 1L SADR1L 8/16 SADR1 0F2D3H SA-ADC result register 1H SADR1H 0F2D4H SA-ADC result register 2L SADR2L 8/16 SADR2 0F2D5H SA-ADC result register 2H...
Page 379 ML610Q111/ML610Q112 User’s Manual Appendix A Registers Symbol Symbol Initial Address Name Size (Byte) (Word) value 0F918H PWMC control register 2 PWCCON2 8/16 PWCCON23 0F919H PWMC control register 3 PWCCON3 0F920H PWMD period register L PWDPL 8/16 0FFH PWDP 0F921H PWMD period register H...
Page 380: Appendix B Package
ML610Q111/ML610Q112 User’s Manual Appendix B Package Dimensions Appendix B Package Dimensions  ML610Q111 Figure B-1 TSSOP20 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Page 381 ML610Q111/ML610Q112 User’s Manual Appendix B Package Dimensions  ML610Q112 FigureB-2 LQFP32 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
Page 382: Appendix C Electrical
ML610Q111/ML610Q112 User’s Manual Appendix C Electrical Characteristics Appendix C Electrical Characteristics  Absolute Maximum Ratings = 0V) Parameter Symbol Condition Rating Unit −0.3 to +7.0 Power supply voltage Ta = 25°C −0.3 to V +0.3 Input voltage Ta = 25°C −0.3 to V...
Page 383 ML610Q111/ML610Q112 User’s Manual Appendix C Electrical Characteristics  DC Characteristics (1/4) (VDD=2.7 to 5.5V, VSS=0V, Ta=−40 to +105°C, unless otherwise specified) Rating Symb Measuring Parameter Condition Unit circuit Min. Typ. Max. CPU : In STOP state ― µA Supply current 1...
Page 384 ML610Q111/ML610Q112 User’s Manual Appendix C Electrical Characteristics  DC Characteristics (2/4) =0V, Ta=−40 to +105°C, unless otherwise specified) =2.7 to 5.5V, V Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. Typ. Typ. Ta=25°C −3.0% +3.0% VLS0 threshold voltage 2.85...
Page 385 ML610Q111/ML610Q112 User’s Manual Appendix C Electrical Characteristics  DC Characteristics (3/4) =0V, Ta=−40 to +105°C, unless otherwise specified) =2.7 to 5.5V, V Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. IOH = −3.0mA, V = 4.5V ― ―...
Page 386 ML610Q111/ML610Q112 User’s Manual Appendix C Electrical Characteristics  Measuring circuit Measuring circuit 1 Measuring circuit 2 (*2) : 1μF Measuring circuit 3 Measuring circuit 4 (*2) (*3) *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins.
Page 387 ML610Q111/ML610Q112 User’s Manual Appendix C Electrical Characteristics  AC Characteristics (Clock) (VDD=2.7 to 5.5V, VSS=0V, Ta=−40 to +105°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Typ. Typ. Ta = -20°C to 85°C 32kHz RC oscillation frequency 32.768...
Page 388 ML610Q111/ML610Q112 User’s Manual Appendix C Electrical Characteristics  AC Characteristics (External Interrupt) =0V, Ta=−40 to +105°C, unless otherwise specified) =2.7 to 5.5V, V Rating Parameter Symbol Condition Unit Min. Typ. Max. Interrupt: Enabled (MIE = 1), 2.5 X 3.5 X ―...
Page 389 ML610Q111/ML610Q112 User’s Manual Appendix C Electrical Characteristics  AC Characteristics (Synchronous Serial Port) =0V, Ta=−40 to +105°C, unless otherwise specified) =2.7 to 5.5V, V Rating Parameter Symbol Condition Unit Min. Typ. Max. When high-speed oscillation is not ― ― µs...
Page 390 ML610Q111/ML610Q112 User’s Manual Appendix C Electrical Characteristics  AC Characteristics (I C Bus Interface: Standard Mode 100kHz) =0V, Ta=−40 to +105°C, unless otherwise specified) =2.7 to 5.5V, V Rating Parameter Symbol Condition Unit Min. Typ. Max. ― ― SCL clock frequency SCL hold time ―...
Page 391 ML610Q111/ML610Q112 User’s Manual Appendix C Electrical Characteristics  Electrical Characteristics of Successive Approximation Type A/D Converter =0V, Ta=−40 to +105°C, unless otherwise specified) =2.7 to 5.5V, V Rating Parameter Symbol Condition Unit Min. Typ. Max.  ― ― Resolution ≤5kΩ，HSCLK=8.192MHz −4...
Page 392: Appendix D Application Circuit Example
ML610Q111/ML610Q112 User’s Manual Appendix D Application Circuit Example Appendix D Application Circuit Example 5.0V uEASE Interface 3.3VOUT VTref TEST TEST RESET_N RESET_N PB0/PWMC ML610Q111 ML610Q112 Reset IC PB1/AIN3 AD Input /SCL /SDA WP SCL SDA C EEPROM A0 A1 A2 : 1μF...
Page 393 Appendix E...
Page 394: Appendix E Check List
[ ] For fail safe in your system, please fill unused program memory area (your program code does not use) with BRK instruction code “0FFH”. Please fill the area with the code “0FFH” when you release a code for LAPIS Semiconductor’s factory programming.
Page 395 ML610Q111/ML610Q112 User's Manual Appendix E Check List •Non-maskable interrupt [ ] The watchdog timer interrupt (WDTINT) is a non-maskable interrupt that does not depend on MIE flag (Refer to Sections 5.2.10. and 5.3 in the User's Manual). Chapter 6 Clock Generation Circuit •Initial System clock...
Page 396 Chapter 24 On-Chip Debug Function • Operating Conditions [ ] Supply a voltage from 2.7V to 5.5V to the VDD pin when programming (erasing and writing) the Flash ROM with LAPIS semiconductor development tool uEASE. [ ] Please do not apply LSIs being used for debugging to mass production.
Page 397 ML610Q111/ML610Q112 User's Manual Appendix E Check List Appendix A SFR (Specific Function Registers) •Initial value Refer to Appendix A in the user’s manual [ ] Please confirm there are some SFRs have undefined initial value at reset ( Appendix C Electrical Characteristics •External capacitors for Power circuits...
Page 398: Revision History
Revision History...
Page 399 ML610Q111/ML610Q112 User’s Manual Revision History Revision History Page Document No. Date Description Previous Current Edition Edition FEUL610Q111-01 Oct. 01, 2013 – – Final edition 1 Add note to WDTMOD register. Corrected a description of PWMF Period 10-26 10-26 register. FEUL610Q111-02 Feb.
Page 400 ML610Q111/ML610Q112 User’s Manual Revision History Added a description of writing to time base counter (LTBR). Changed from “Auto reload timer” to “Continuous mode”. Changed florm “One-shot timer mode” to “One-shot mode .” 8-6 to 8-6 to Added note of timer n data register (TMnD).
Page 401 ML610Q111/ML610Q112 User’s Manual Revision History Removed a description of multi master of I20BB bit. 13-9 13-9 Removed a description of clock synchronization of I20ER bit.. Remove a description of multi master of I20ER bit.. 13-12 13-12 Added a description of I20ER bit.
Page 402 ML610Q111/ML610Q112 User’s Manual Revision History Added note for using a port as comparator 22-9 22-10 input. Corrected the condition of the rewrite count of data flash memory. 23-1 23-1 (wrong) -20 to 75°C(Ta） (correct) -20 to 85°C(Ta） 23-4 23-4 Added note of the 1-word writing operation.

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Ml610q112

Lapis ML610Q111 User Manual

Chapter 1 Overview

Chapter 2 CPU and Memory Space

Chapter 3 Reset Function

Chapter 4 MCU Control Function

Chapter 5 Interrupts (Ints)

Chapter 6 Clock Generation Circuit

Chapter 7 Time Base Counter

Chapter 8 Timers

Chapter 9 Watchdog Timer

Chapter 10 PWM

Chapter 11 Synchronous Serial Port

Chapter 12 UART

Chapter 13 I2C Bus Interface Master

Chapter 14 I2C Bus Interface Slave

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Summary of Contents for Lapis ML610Q111