MC9S12DT256 Device User Guide — V03.07
1
SS
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
9
MOSI
PORT DATA
(OUTPUT)
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
In Table A-19 the timing characteristics for master mode are listed.
Num
Characteristic
1
SCK Frequency
1
SCK Period
2
Enable Lead Time
3
Enable Lag Time
4
Clock (SCK) High or Low Time
5
Data Setup Time (Inputs)
6
Data Hold Time (Inputs)
9
Data Valid after SCK Edge
10
Data Valid after SS fall (CPHA=0)
11
Data Hold Time (Outputs)
12
Rise and Fall Time Inputs
13
Rise and Fall Time Outputs
120
1
2
4
4
5
6
2
MSB IN
2
MASTER MSB OUT
Figure A-7 SPI Master Timing (CPHA=1)
Table A-19 SPI Master Mode Timing Characteristics
12
13
12
13
BIT 6 . . . 1
11
BIT 6 . . . 1
MASTER LSB OUT
Symbol
Min
f
1/2048
sck
t
2
sck
t
—
lead
t
—
lag
t
—
wsck
t
8
su
t
8
hi
t
—
vsck
t
—
vss
t
20
ho
t
—
rfi
t
—
rfo
3
LSB IN
PORT DATA
Typ
Max
—
1/2
—
2048
1/2
—
1/2
—
1/2
—
—
—
—
—
—
30
—
15
—
—
—
8
—
8
Unit
f
bus
t
bus
t
sck
t
sck
t
sck
ns
ns
ns
ns
ns
ns
ns