Motorola MC9S12DT256 User Manual page 54

MC9S12DT256 Device User Guide — V03.07
Pin Name Pin Name
Funct. 1 Funct. 2
EXTAL —
XTAL —
RESET —
TEST —
VREGEN —
XFC —
BKGD TAGHI
PAD[15] AN1[7]
PAD[14:8] AN1[6:0]
PAD[7] AN0[7]
PAD[6:0] AN0[6:0]
ADDR[15:8]/
PA[7:0]
DATA[15:8]
ADDR[7:0]/
PB[7:0]
DATA[7:0]
PE7 NOACC
PE6 IPIPE1
PE5 IPIPE0
PE4 ECLK
PE3 LSTRB
PE2 R/W
PE1 IRQ
PE0 XIRQ
PH7 KWH7
PH6 KWH6
PH5 KWH5
54
Pin Name Pin Name Pin Name
Funct. 3 Funct. 4
— —
— —
— —
— —
— —
— —
MODC —
ETRIG1 —
— —
ETRIG0 —
— —
— —
— —
XCLKS —
MODB —
MODA —
— —
TAGLO —
— —
— —
— —
SS2 —
SCK2 —
MOSI2 —
Internal Pull
Power
Funct. 5 Supply
CTRL
— VDDPLL NA
— VDDPLL NA
— VDDR
None
— N.A. NA
— VDDX NA
— VDDPLL NA
Always
— VDDR
Up
— VDDA
None
— VDDA
None
— VDDA
None
— VDDA
None
— VDDR
PUCR
— VDDR
PUCR
— VDDR
PUCR
While RESET
— VDDR
While RESET
— VDDR
— VDDR
PUCR
— VDDR
PUCR
— VDDR
PUCR
— VDDR PUCR
— VDDR PUCR
PERH/
— VDDR
PPSH
PERH/
— VDDR
PPSH
PERH/
— VDDR
PPSH
Resistor
Reset
State
NA
Oscillator Pins
NA
None External Reset
NA Test Input
NA
Voltage Regulator Enable Input
NA
PLL Loop Filter
Background Debug, Tag High, Mode
Up
Input
Port AD Input, Analog Input AN7
of ATD1, External Trigger Input of
None
ATD1
Port AD Inputs, Analog Inputs
None
AN[6:0] of ATD1
Port AD Input, Analog Input AN7 of
None
ATD0, External Trigger Input of ATD0
Port AD Inputs, Analog Inputs
None
AN[6:0] of ATD0
Disabled Port A I/O, Multiplexed Address/Data
Disabled Port B I/O, Multiplexed Address/Data
Up Port E I/O, Access, Clock Select
pin is low:
Port E I/O, Pipe Status, Mode Input
Down
pin is low:
Port E I/O, Pipe Status, Mode Input
Down
Up Port E I/O, Bus Clock Output
Up Port E I/O, Byte Strobe, Tag Low
Up Port E I/O, R/W in expanded modes
Up
Port E Input, Maskable Interrupt
Up Port E Input, Non Maskable Interrupt
Disabled Port H I/O, Interrupt, SS of SPI2
Disabled Port H I/O, Interrupt, SCK of SPI2
Disabled Port H I/O, Interrupt, MOSI of SPI2
Description