Spi; Master Mode; Figure A-6 Spi Master Timing (Cpha=0); Table A-18 Measurement Conditions - Motorola MC9S12DT256 User Manual

A.7 SPI
This section provides electrical parametrics and ratings for the SPI.
In Table A-18 the measurement conditions are listed.
Description
Drive mode
Load capacitance C
LOAD,
on all outputs
Thresholds for delay
measurement points

A.7.1 Master Mode

In Figure A-6 the timing diagram for master mode with transmission format CPHA=0 is depicted.
1
SS
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.

Table A-18 Measurement Conditions

2 1
4
4
5 6
2
BIT 6 . . . 1
MSB IN
10
2
BIT 6 . . . 1
MSB OUT

Figure A-6 SPI Master Timing (CPHA=0)

MC9S12DT256 Device User Guide — V03.07
Value
full drive mode
50
(20% / 80%) VDDX
12
12
LSB IN
9
Unit
—
pF
V
13 3
13
11
LSB OUT
119