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A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
≤ V
≤ V
≤ V
V
SSA
RL
IN
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Conditions are shown in Table A-4 unless otherwise noted
Num C
Reference Potential
1
D
2
C Differential Reference Voltage
3
D ATD Clock Frequency
ATD 10-Bit Conversion Period
4
D
Conv, Time at 2.0MHz ATD Clock f
ATD 8-Bit Conversion Period
5
D
Conv, Time at 2.0MHz ATD Clock f
D Recovery Time (V
6
7
P
Reference Supply current 2 ATD blocks on
8
P
Reference Supply current 1 ATD block on
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
A.2.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R
≤ V
. This constraint exists since the sample buffer amplifier can not drive
RH
DDA
Table A-8 ATD Operating Characteristics
Rating
1
Clock Cycles
Clock Cycles
=5.0 Volts)
DDA
MC9S12DT256 Device User Guide — V03.07
Symbol
Min
V
V
Low
RL
High
V
V
RH
DDA
V
-V
4.50
RH
RL
f
0.5
ATDCLK
2
N
CONV10
T
ATDCLK
CONV10
2
N
CONV8
T
ATDCLK
CONV8
t
REC
I
REF
I
REF
Typ
V
SSA
/2
V
5.00
14
7
12
6
0.750
0.375
Max
Unit
/2
V
DDA
V
DDA
5.25
V
2.0
MHz
28
Cycles
µs
14
26
Cycles
µs
13
µs
20
mA
mA
S
99
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