Motorola MC9S12DT256 User Manual page 114

MC9S12DT256 Device User Guide — V03.07
The loop bandwidth f
C
typical values are 50. ζ = 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f =10kHz:
C
2 π n f ⋅ ⋅
R = ---------------------------- -
The capacitance C can now be calculated as:
s
C
s
The capacitance C should be chosen in the range of:
p
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock f
deviation from the reference clock f
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.
114
should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10,
2 ζ f ⋅ ⋅
ref
f < ------------------------------------------
C
⎛
π ⋅ ζ
+ 1 +
⎝
f
VCO
n = ------------ - = 2
f
ref
⋅
C
= 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ
K
Φ
2
2 ζ ⋅
0.516
≈ -------------- - ζ
= --------------------- -
⋅
π f ⋅ ⋅
R f
C C
⁄ ≤
C 20 C
s p
is measured and input voltage to the VCO is adjusted
ref
f
1
→ ------------- - ζ
----- - f <
C
10 4 10
⎞
2
ζ
f < 25kHz
⎠
C
⋅ ( )
synr + 1
= 50
= 5.19nF =~ 4.7nF
( )
; = 0.9
R
≤ ⁄
C 10
C = 470pF
s
p
ref
( )
; = 0.9
⋅
, the
cmp